Layout structure of bit line sense amplifiers for a...

Details Layout structure of bit line sense amplifiers for a... Layout structure of bit line sense amplifiers for a...

2011-01-11

2011-01-11

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Format or disposition of elements

C365S205000, C365S049110, C365S154000, C365S189150, C365S189020, C365S189050, C365S190000, C365S202000, C365S207000, C365S210130

Reexamination Certificate

active

07869239

ABSTRACT:
A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier.

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