Semiconductor device manufacturing: process – Having selenium or tellurium elemental semiconductor component
Reexamination Certificate
2011-08-09
2011-08-09
Smith, Bradley K (Department: 2894)
Semiconductor device manufacturing: process
Having selenium or tellurium elemental semiconductor component
C438S587000, C438S128000, C438S109000, C257SE21068, C257SE23029, C257S246000
Reexamination Certificate
active
07993961
ABSTRACT:
A line layout structure and method in a semiconductor memory device having a hierarchical structure are provided. In a semiconductor memory device having a global word line and a local word line, and a global bit line and a local bit line, and individually disposing all of the global word line, the local word line, the global bit line and the local bit line at conductive layers among at least three layers; at least two of the global word line, the local word line, the global bit line and the local bit line are together disposed in parallel on one conductive layer. Signal lines constituting a semiconductor memory device are disposed in a hierarchical structure, whereby a semiconductor memory device advantageously having high integration, high speed and high performance may be obtained.
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Kang Sang-Beom
Kim Du-Eung
Oh Hyung-Rok
Karimy Mohammad T
Samsung Electronics Co,. Ltd.
Smith Bradley K
Volentine & Whitt PLLC
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