Layout structure for sub word line drivers and method thereof

Details Layout structure for sub word line drivers and method thereof Layout structure for sub word line drivers and method thereof

2008-04-15

2008-04-15

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S063000, C365S230030

Reexamination Certificate

active

07359280

ABSTRACT:
A layout structure for sub word line drivers and method thereof. The example layout structure may include at least one N-channel transistor arrangement having a cross sectional width and a cross sectional length, the N-channel transistor arrangement oriented such that the cross sectional length extends along a first direction, the first direction oriented along a sub word line driver from a first sub array block to a second sub array block. The example method may arrange the at least one N-channel transistor between the first and second sub array blocks.

REFERENCES:
patent: 5604697 (1997-02-01), Takahashi et al.
patent: 6236617 (2001-05-01), Hsu et al.
patent: 7016214 (2006-03-01), Kawamata et al.

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