Layout structure for a flip chip semiconductor integrated...

Details Layout structure for a flip chip semiconductor integrated... Layout structure for a flip chip semiconductor integrated...

2005-01-11

2005-01-11

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Flip chip

C257S738000, C257S207000, C257S208000, C257S211000

Reexamination Certificate

active

06841886

ABSTRACT:
There is disclosed a flip chip semiconductor integrated circuit, which comprises an internal cell, an I/O buffer as an interface between the internal cell and an external unit, a solder ball, a GND or power supply wire, and an I/O buffer unit arranged on a chip. In this case, the components except the I/O buffer unit are formed in a unit and arranged on the chip, and the I/O buffer unit includes a signal solder ball for transferring signals with the external unit, an I/O buffer having a signal terminal connected to the signal solder ball, a first I/O buffer GND wire connected to a GND terminal of the I/O buffer, and a first I/O buffer power supply wire connected to a power supply terminal of the I/O buffer.

REFERENCES:
patent: 6498396 (2002-12-01), Arimoto
patent: 07-022510 (1995-01-01), None
patent: 09-107048 (1997-04-01), None
patent: 11-150204 (1999-06-01), None
patent: 2000-050240 (2000-02-01), None
patent: 2000-150802 (2000-05-01), None

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