Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2006-08-29
2006-08-29
Lee, Eddie (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S369000, C257S372000, C257S373000, C257S210000, C257S206000, C257S403000, C257S374000, C257S355000, C257S299000, C257S544000, C257S216000, C257S349000, C257S536000, C257S401000, C257S296000
Reexamination Certificate
active
07098512
ABSTRACT:
Layout patterns for the deep well region to facilitate routing the body-bias voltage in a semiconductor device are provided and described. The layout patterns include a diagonal sub-surface mesh structure, an axial sub-surface mesh structure, a diagonal sub-surface strip structure, and an axial sub-surface strip structure. A particular layout pattern is selected for an area of the semiconductor device according to several factors.
REFERENCES:
patent: 5447876 (1995-09-01), Moyer et al.
patent: 6048746 (2000-04-01), Burr
patent: 6087892 (2000-07-01), Burr
patent: 6091283 (2000-07-01), Murgula et al.
patent: 6169310 (2001-01-01), Kalnitsky et al.
patent: 6218708 (2001-04-01), Burr
patent: 6303444 (2001-10-01), Burr
patent: 6489224 (2002-12-01), Burr
patent: 6936898 (2005-08-01), Pelham et al.
patent: 2001/0028577 (2001-10-01), Sung et al.
patent: 0624909 (1994-11-01), None
Burr James B.
Pelham Mike
Im Junghwa
Lee Eddie
Transmeta Corporation
LandOfFree
Layout patterns for deep well region to facilitate routing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Layout patterns for deep well region to facilitate routing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Layout patterns for deep well region to facilitate routing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3662311