Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2011-01-04
2011-01-04
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07865848
ABSTRACT:
A method of layout optimization containing parameterized cells includes reading a physical design containing parameterized cells, creating a new version for each of usage of a given parameterized cell. The method optimizes physical design shapes of each new version of the parameterized cell by assigning variables to parameters of the parameterized cell according to a desired objective. Then, the method updates the parameters of each new version of the parameterized cell and replaces each new version of the parameterized cell with an instance of the parameterized cell having updated parameters. The method can optionally adjust physical design shapes based on constraints related to the parameters.
REFERENCES:
patent: 5802349 (1998-09-01), Rigg et al.
patent: 7007258 (2006-02-01), Li
Gernhoefer Veit
Gray Michael S.
Guzowski Matthew T.
Hibbeler Jason D.
Runyon Stephen L.
Chiang Jack
Gibb I.P. Law Firm LLC
International Business Machines - Corporation
Kotulak, Esq. Richard M.
Tat Binh C
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