Layout optimization of integrated trench VDMOS arrays

Details Layout optimization of integrated trench VDMOS arrays Layout optimization of integrated trench VDMOS arrays

2006-07-04

2006-07-04

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S330000, C257S341000, C257S628000, C438S259000, C438S270000

Reexamination Certificate

active

07071513

ABSTRACT:
An economical integration of trench VDMOS devices into a conventional BCD process is provided, with the optimization of key aspects of the device layout for low Rds(on)area. Specifically, trench orientation, array geometry, the number of source cells between drain pickups and drain-source spacing are independently optimized. In one embodiment of the invention, the optimized device utilizes a rectangular cell array with an elongation ratio in the range of 5/3–7/3, with a ratio of 5/3 being preferred, and a cell orientation at 45° with respect to the wafer flat on a 100 wafer.

REFERENCES:
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patent: 2003/0146489 (2003-08-01), Shimizu
patent: 2004/0063291 (2004-04-01), Williams et al.
patent: 2005/0161735 (2005-07-01), Aoki et al.
M.G.L. van den Heuvel et al., “An improved method for determining the inversion layer mobility of electrons in trench MOSFETs,” (student paper),Proc. ISPSD,(2003), 4 pages in length.

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