Layout of well contacts and source contacts of a semiconductor d

Details Layout of well contacts and source contacts of a semiconductor d Layout of well contacts and source contacts of a semiconductor d

1999-04-01

2000-05-16

Hardy, David

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257773, H01L 2941

Patent

active

060640995

ABSTRACT:
There is described a semiconductor device intended to increase a degree of integration of transistor without impairing a desired element characteristic. An n-type source region and an n-type drain region are formed in a p-well which acts as a substrate region of an NMOS transistor. Further, there are formed a first contact plug to be electrically connected to the n-type source region and a second contact plug to be electrically connected to the n-type drain region. The n-type source region is provided so as to become short-circuited with the p-well. The n-type drain region is provided so as not to become short-circuited with the p-well. The n-type source region is formed so as to become smaller than the n-type drain region.

REFERENCES:
patent: 4621276 (1986-11-01), Malhi
patent: 4647956 (1987-03-01), Shrivastava et al.
patent: 4905073 (1990-02-01), Chen et al.
patent: 5753944 (1998-05-01), Sakaue
patent: 5920089 (1999-07-01), Kanazawa et al.

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