Layout of power device

Details Layout of power device Layout of power device

2007-01-23

2009-08-04

Kik, Phallaka (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C257S207000, C257S341000, C257S401000, C257S500000, C257S578000, C257S691000, C330S297000, C330S123000, C330S127000, C330S199000

Reexamination Certificate

active

07571415

ABSTRACT:
A layout of a power device is provided. The layout includes a substrate, a unit array, a plurality of first, second, third and fourth signal paths, and a first, second, third and fourth port. The unit array with a plurality of rows is disposed on the substrate. Each row of the unit array includes a plurality of units. The first and second signal paths on the substrate are disposed on a first side and a second side of corresponding odd-numbered rows of the unit array. The third and the fourth signal paths on the substrate are disposed above a corresponding row of the unit array. The first to fourth ports on the substrate are electrically connected to the first to fourth signal paths respectively.

REFERENCES:
patent: 3863232 (1975-01-01), Johnson et al.
patent: 6356484 (2002-03-01), Dosaka et al.
patent: 6448858 (2002-09-01), Helms et al.
patent: 6833756 (2004-12-01), Ranganathan
patent: 2005/0088881 (2005-04-01), Miki et al.
patent: 2006/0108694 (2006-05-01), Hung et al.
patent: 1447592 (2003-10-01), None

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