Layout of a folded bitline DRAM with a borderless bitline

Details Layout of a folded bitline DRAM with a borderless bitline Layout of a folded bitline DRAM with a borderless bitline

2003-06-04

2004-08-24

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000, C257S302000

Reexamination Certificate

active

06781181

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a dynamic random access memory (DRAM). In particular, the present invention relates to a DRAM with vertical transistors and deep trench capacitors.
2. Description of the Related Art
With the wide application of integrated circuits (ICs), several kinds of semiconductor devices with higher efficiency and lower cost are produced based on different objectives. DRAM is such an important semiconductor device in the information and electronics industry.
Most of the DRAMs nowadays have one transistor and one capacitor in one DRAM cell. The memory capacity of the DRAM has reached 64 megabits, and can even reach 256 megabits. Therefore, under the increasing of the integration it is needed to shrink the size of the memory cell and the transistor so as to manufacture the DRAM with higher memory capacity and higher processing speed. A 3-D capacitor structure itself can reduce its occupation area in the semiconductor substrate, so the 3-D capacitor, such as a deep trench capacitor, is applied to the fabrication of the DRAM of 64 megabits and above. Referring to a traditional plane transistor, it covers quite a few areas of the semiconductor substrate and cannot satisfy the request of high integration. Therefore, a vertical transistor which can save space is a trend of fabrication of a memory unit.
One of the most used DRAM cell array is an open bitline structure, in which each memory cell is arrayed with a matrix.
Another frequently used DRAM cell array is a folded bitline structure, as shown in FIG.
9
. Each memory cell, using label
10
as an example, comprises a transistor
12
, a storage capacitor
14
, a bitline
22
, a wordline
18
and a passing wordline
20
. When an approproate voltage is applied to the bitline
22
and the wordline
18
, data can be written into or read from the capacitor
14
. When an output volage is applied to the memory cell
10
covering the connecting wordline
18
and the passing wordline
20
, bitlines
22
and
24
are switched to differential sense amplifier.
FIG. 10
is a cross-sectional view of the memory cell
10
in FIG.
9
. The wordline
18
is also used as a gate of the transistor
12
. The passing wordline
20
is located over the thick oxide layer
36
, and works no function for operation of the memory cell
10
. The bitline
22
is connected to a source
40
of the transistor
12
through a contact window
38
. A drain
42
of the transistor
12
is connected to the deep trench capacitor
44
through a buried strap
41
.
However, such structure of the memory cell
10
has some challenges as described below. The outdiffusion of the dopants contained in the buried strap
41
may induce the short channel effect. Therefore, it is impossible to decrease the distance between the wordline
18
and deep trench capacitor
44
to increase the integration of the DRAM.
With the enhancement of the memory capacity, a DRAM with more compact transistors and deep trench capacitors is needed to satisfy the requirements of memory capacity.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a DRAM cell array with a vertical transistor and a deep trench capacitor, so as to release the limitation from the wordline to deep trench to increase the integration of the DRAM.
Another object of the present invention is to provide an open bitline DRAM with a vertical transistor and a deep trench capacitor, so as to increase the integration of the DRAM.
Another object of the present invention is to provide a folded bitline DRAM with a vertical transistor and a deep trench capacitor, so as to increase the integration of the DRAM.
Another object of the present invention is to provide a folded DRAM with a vertical transistor, a deep trench capacitor and a borderless bitline contact window, so as to increase the integration of the DRAM.
The present invention provides a DRAM cell with a vertical transistor and a deep trench capacitor. In the DRAM cell, a deep trench capacitor comprising an upper electrode, an insulating film and a storage electrode is desposed in a substrate; a gate of the vertical transistor is disposed over the deep trench capacitor; an ion doped layer is disposed between the gate and the upper electrode of the capacitor; an insulating layer is disposed between the gate and the ion doped layer; a gate insulating layer of the vertical transistor is disposed on a sidewall of the gate; a channel region is located beside the gate insulating layer in the substrate; a source is disposed on a sidewall of the ion doped layer and on one side of the vertical channel region; and a common drain is disposed on the other side of the vertical channel region. Moreover, a shallow trench isolation is disposed on another sidewall of the ion doped layer.
The present invention provides an open bitline DRAM with straight wordlines, wherein each DRAM cell is as mentioned above, the deep trench capacitors are arranged in a matrix in the substrate.
The present invention provides an open bitline DRAM with zigzag wordlines, wherein each DRAM cell is as mentioned above. The deep trench capacitors belonging to different rows are arranged with a shift.
The present invention provides a folded DRAM, wherein each DRAM cell is as mentioned above.
The present invention provides a folded DRAM with borderless bitline contact window, wherein each DRAM cell is as mentioned above.


REFERENCES:
patent: 4694428 (1987-09-01), Matsumura et al.
patent: 5831301 (1998-11-01), Horak et al.
patent: 6034879 (2000-03-01), Min et al.
patent: 6339239 (2002-01-01), Alsmeier et al.

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