Layout methodology and system for automated place and route

Details Layout methodology and system for automated place and route Layout methodology and system for automated place and route

2005-08-23

2005-08-23

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C005S008000, C005S010100, C005S012100, C005S013000, C005S014000

Reexamination Certificate

active

06934924

ABSTRACT:
A new simple novel Layout methodology for high integration VLSI chip is proposed, which is reduced dramatically the complexity, the cost and the schedule for implementing a complex chip such as System On a Chip (SOC) that required hierarchical layout implementation. A set of rules is provided for the place and route process.

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