Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-09-29
2008-11-04
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07448011
ABSTRACT:
Cells with the same logic and similar driving capability among cells arranged on a substrate of a semiconductor integrated circuit are made into a format comprising terminals at the same position in the same-sized cell frame, and within cells in such a format, by arranging other cells in a redundant region of cell frame in a cell with low driving capability, wiring modification operation is reduced in layout of a semiconductor integrated circuit and efficiency of circuit design is improved, preventing chip size from being redundantly large.
REFERENCES:
patent: 5459673 (1995-10-01), Carmean et al.
patent: 5663662 (1997-09-01), Kurosawa
patent: 6093214 (2000-07-01), Dillon
patent: 6324671 (2001-11-01), Ratzel et al.
patent: 6487702 (2002-11-01), Lin et al.
patent: 6516456 (2003-02-01), Garnett et al.
patent: 6574786 (2003-06-01), Pohlenz et al.
patent: 6591407 (2003-07-01), Kaufman et al.
patent: 6593792 (2003-07-01), Fujii
patent: 6606736 (2003-08-01), Kobayashi et al.
patent: 6691294 (2004-02-01), Law
patent: 6748579 (2004-06-01), Dillon et al.
patent: 6904581 (2005-06-01), Oh
patent: 6978431 (2005-12-01), Hirakimoto et al.
patent: 7137094 (2006-11-01), Tien
patent: 7208350 (2007-04-01), Kawashima et al.
patent: 7260803 (2007-08-01), Lakshmanan et al.
patent: 7272809 (2007-09-01), Becker et al.
patent: 2004/0064800 (2004-04-01), Korobkov
patent: 2005/0044522 (2005-02-01), Maeda
patent: 2005/0108671 (2005-05-01), Becker et al.
patent: 2006/0015835 (2006-01-01), Huang et al.
patent: 2007/0038968 (2007-02-01), Braun et al.
patent: 2007/0061769 (2007-03-01), Kumagai
patent: 2007/0130552 (2007-06-01), Inoue
patent: 2007/0150849 (2007-06-01), Haruki
patent: 8-181216 (1996-07-01), None
patent: 2003-282711 (2003-10-01), None
Dinh Paul
Fujitsu Limited
Sandoval Patrick
Staas & Halsey , LLP
LandOfFree
Layout method of semiconductor integrated circuit and cell... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Layout method of semiconductor integrated circuit and cell..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Layout method of semiconductor integrated circuit and cell... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4030223