Layout method of semiconductor circuit, program and design...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing

Reexamination Certificate

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Reexamination Certificate

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07934178

ABSTRACT:
A method of a layout a semiconductor circuit has obtaining transistor characteristic information on the basis of layout information about regions formed with transistors, obtaining a polynomial expression representing a relationship between characteristic values of a circuit including of the transistors and the transistor characteristic information, calculating a plurality of characteristic values corresponding to plural sets of transistor characteristic information by use of the polynomial expression, selecting part of the plurality of characteristic values on the basis of a restriction about the characteristic values, the layout information or the transistor characteristic information; and obtaining the transistor characteristic information or the layout information corresponding to the selected characteristic values.

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Japanese Notification of Reasons for Rejection, English-language translation, mailed Dec. 21, 2010 for corresponding Japanese Application No. 2006-300507.
Fujita, Tomohiro “Statistical Timing Analysis Method for Large Scale Integrated Circuit”, DA Symposium 2000, Information Processing Society of Japan, vol. 2000, No. 8, Jul. 17, 2000, pp. 91-96.

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