Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-08-28
2003-12-02
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S173000, C257S373000, C257S355000, C257S360000
Reexamination Certificate
active
06657264
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and a layout method and more particularly to a device and method of latch-up prevention in an electrostatic discharge (ESD) circuit of the semiconductor memory device.
2. Description of the Related Art
The reduction in size of semiconductor memory devices by very large scale integration has brought about reliability problems, such as electrostatic discharge (ESD), latch-up, oxide layer break down, etc. The structure of a bulk CMOS device has a parasitic bipolar junction transistor (BJT), which generally remains at a turn-off state but may be turned on by an external voltage change such as ESD or noise. Such condition is called a ‘latch-up’. Latch-ups cause erroneous circuit operations and may cause circuit break-down. The frequency of latch-ups is low as long as there is no error in current design rules, for instance in the layout structure of a device. Latch-up is more of a problem when a gate oxide layer of the CMOS device gets thinner and a light doped drain (LLD) structure is utilized. ESD latch-up prevention technology is needed to ensure reliability of the device.
One ESD latch-up prevention circuit is constructed with transistors and a P+ guard ring which turn on to reduce positive
egative stress and exhaust ESD current. The prevention circuit includes a semiconductance controlled rectifier (SCR) having a PNPN structure artificially constructed as an ESD prevention circuit and used as a trigger circuit for operations of vertical and horizontal parasitic BJT, thereby exhausting ESD current. However, such circuit exhibits a weak latch-up characteristic due to the artificial construction of the SCR.
FIG. 1
shows a conventional layout of a main chip which includes a cell array
40
arranged in the main chip
100
, an ESD prevention transistor
10
connected to a pad
20
, and a peripheral circuit
30
neighboring the cell array
40
. Generally, a guard ring (not shown in
FIG. 1
) should be disposed next to the peripheral circuit
30
to prevent latch-up. To better absorb carriers (holes or electrons) which cause latch-up, the guard ring should be larger. However, a large guard ring requires more chip real estate and compromises circuit density of the chip.
FIGS. 2 and 3
illustrate an ESD prevention circuit in connection with an input pad
20
. The circuit has ESD prevention transistor
10
which is an NMOS transistor
10
disposed between the input pad
20
and an external input
1
.
FIG. 3
is a schematic view of FIG.
2
. ESD can be prevented by a junction diode between NMOS drain
14
connected to the input pad
20
and P-type substrate (P-SUB)
11
, and a lateral BJT between NMOS drain
13
and P-SUB
11
. However, there is no reliable prevention means against latch-ups connected to the input pad
20
.
FIG. 4
is an ESD prevention circuit having a SCR
50
.
FIG. 5
is a schematic view of FIG.
4
. As shown in
FIGS. 4 and 5
, the pad
20
is simultaneously connected to a PN junction installed in a NWELL guard ring
60
, and an NMOS drain
53
is connected to the pad
20
through the NWELL
60
. A vertical PNP transistor is formed among PMOS
52
, NWELL
60
and P-SUB
11
, and a lateral NPN transistor among NWELL
60
, P-SUB
11
and NMOS source
54
. When ESD current flows to the circuit, the SCR
50
is turned on by a voltage drop across resistance Rw so as to sufficiently exhaust the ESD current. However, a disadvantage of the SCR
50
is a weak latch-up characteristic.
A need therefore exists for a semiconductor device for effectively solving the aforementioned problems.
SUMMARY OF THE INVENTION
A layout method of a latch-up prevention circuit of a semiconductor memory device is provided which includes the steps of: arranging a plurality of pads at an edge of the device; and
arranging a guard ring beneath the plurality of pads.
According to an aspect of the invention, the layout method further includes a plurality of ESD protection transistors disposed axially along the direction as the plurality of pads and between the plurality of pads and the edge of the device, and the guard ring is connected to the edge of the device along the parallel direction as the plurality of pads.
A layout method of a latch-up prevention circuit of a semiconductor memory device is provided which includes the steps of: arranging a cell array at substantially the middle of the device; placing peripheral circuits next to both sides of the cell array; placing a plurality of pads on both sides of the cell array between the peripheral circuits and both edges of the device; and arranging guard rings beneath the plurality of pads.
According to an aspect of the invention, the layout method further includes a plurality of ESD protection transistors along the parallel direction as the plurality of pads between the plurality of pads and an edge of the device, and the guard ring is connected to an edge of the device along the parallel direction as the plurality of pads.
A semiconductor memory device is provided which includes: a cell array disposed substantially at the middle of the device; a plurality of peripheral circuits disposed next to both sides of the cell array; a plurality of pads disposed at all sides of the cell array between the peripheral circuits and edges of the device; and guard rings disposed beneath the plurality of pads.
According to an aspect of the invention, the device further includes a plurality of ESD protection transistors disposed axially along the axial direction as the plurality of pads and between the plurality of pads and an edge of the device, and each of the guard rings is connected each other.
According to an aspect of the invention, each of the guard rings is a NWELL guard ring, and connected to one of a supply voltage and ground.
REFERENCES:
patent: 5637900 (1997-06-01), Ker et al.
patent: 5804861 (1998-09-01), Leach
patent: 5828110 (1998-10-01), Wollesen
patent: 5920096 (1999-07-01), Lee
patent: 6028341 (2000-02-01), Tai et al.
patent: 6337506 (2002-01-01), Morishita et al.
patent: 362188363 (1987-08-01), None
patent: 2000-040751 (2000-08-01), None
Cho Beak-Hyung
Kwak Choong-Keun
F. Chau & Associates
Mondt Johannes
Samsung Electronics Co. LTD
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