Layout method of a semiconductor memory device

Details Layout method of a semiconductor memory device Layout method of a semiconductor memory device

2007-04-25

2008-12-02

Mai, Son L (Department: 2827)

Static information storage and retrieval

Format or disposition of elements

C365S063000, C365S148000, C365S163000

Reexamination Certificate

active

07460386

ABSTRACT:
The layout method for a semiconductor device includes locating a plurality of first bit line selection circuits at a first side of a variable resistive memory cell block, and locating a plurality of second bit line selection circuits at a second side of the variable resistive memory cell block opposite the first side. The method further includes connecting the first bit line selection circuits with respective odd-numbered local bit lines of the variable resistive memory cell block, and connecting the second bit line selection circuits with respective even-numbered local bit lines of the variable resistive memory cell block. The method still further includes selectively connecting respective odd-numbered local bit lines to a global bit line using the first bit line selection circuits, and selectively connecting respective even-numbered local bit lines to the global bit line using the second bit line selection circuits.

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