Layout method for semiconductor integrated circuit, layout...

Details Layout method for semiconductor integrated circuit, layout... Layout method for semiconductor integrated circuit, layout...

2004-12-29

2008-10-14

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07437699

ABSTRACT:
When carrying out placement and routing processing on a layout object circuit using circuit connectivity information and power supply information, a first step of specifying a power supply terminal corresponding to a signal terminal designated for input level fixation by the circuit connectivity information on the basis of terminal correspondence information, a second step of specifying a power supply voltage corresponding to the power supply terminal specified at the first step on the basis of the power supply information, and a third step of routing a power supply line of the power supply voltage specified at the second step to the signal terminal for input level fixation and thus connecting them, are carried out. Thus, connection processing to connect the signal terminal for input level fixation and the power supply line can be automatically carried out and a design period for a multi-power supply semiconductor integrated circuit can be reduced.

REFERENCES:
patent: 6496964 (2002-12-01), Inui et al.
patent: 6993740 (2006-01-01), Bergamaschi et al.
patent: 7117459 (2006-10-01), Tanimoto et al.
patent: 7120885 (2006-10-01), Nakayama et al.
patent: 2002-015018 (2002-01-01), None
patent: 2003-345853 (2003-12-01), None

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