Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-08-16
2010-10-05
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07810051
ABSTRACT:
A layout method for a layout design of a circuit includes a simulation step carrying out a simulation of the circuit, a specifying step specifying a maximum current value to flow between terminals of each of elements of the circuit and specifying a shape of each of the elements, and a layout composing step automatically creating and completing a layout of the elements so as to satisfy an electro migration rule, based on the specified maximum current value and shape of each of the elements.
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Chiang Jack
Fujitsu Patent Center
Fujitsu Semiconductor Limited
Tat Binh C
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