Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-03-21
2004-02-10
Lam, Tuan T. (Department: 2816)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06691293
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a layout instrument that lays out cells, etc., of a semiconductor integrated circuit, a layout method thereof and a recording medium that stores a program for determining the layout of a semiconductor integrated circuit.
2. Description of the Related Art
In a layout design of a large-scale integrated circuit (LSI), a layering layout method is used to enhance the efficiency of a design work. In the layering design method, the top module of the LSI is divided into logic that connects the sub-modules
11
,
12
,
13
, . . . , and the sub-modules
11
,
12
. . . , as shown in FIG.
1
. Next, which region of a chip each of the sub-modules
11
,
12
. . . , occupies is determined, and an internal layout of each sub-module
11
,
12
. . . , is determined independently. There are two methods for connecting each of the sub-modules
11
,
12
. . . : the method for connecting them before determining the internal layout and the method for connecting them after determining the internal layout. Such methods as this, if adopted, would have the following advantages.
(1) The interior of each module can be designed in parallel.
(2) Once the specifications for the interfaces of the sub-modules have been determined, the design of the sub-modules can be carried out even if no logical design of the interior of some sub-modules has been determined yet.
(3) The amount of data to be dealt with in large-scale integrated circuit (LSI) is enormously large, but the amount of data to be dealt with at one time can be reduced by handling the interior of a sub-module as a black box.
There is a delay restriction as the restriction that must be satisfied when designing synchronous LSI.
FIG. 2
is a diagram showing the delay restriction of synchronous LSI. In synchronous LSI, when a flip-flop receives a clock signal, a signal begins to be transmitted, and this signal passes through the cells
22
,
23
,and
24
, and must be captured by the flip-flop
25
before the next clock arrives at the flip-flop
25
. In order for LSI to work at a specified clock frequency, the time by which the signal arrives at the final flip-flop
25
must be kept within the delay restriction time. The longer the length of a wire, the greater the delay. So, the length of the wire should be made short at the part in which a severe delay restriction is imposed so that a layout that satisfies the delay restriction can be determined.
If a layout is only determined when carrying out a layering design without considering the delay of a signal, the layout in a particular sub-module can be determined without regard to the influence of the other sub-modules, thus making it possible to easily carry out a layering design.
However, when the delay of the signal needs to be taken into consideration, the delay of signals in the other sub-modules must also be taken into consideration. For instance, consider the path that starts from a flip-flop
32
in the sub-module
31
and arrives at a flip-flop
34
in the sub-module
33
. When a layout in the sub-module
31
is determined, if cannot be determined to what extent the delay of the sub-module
31
can be allowed without considering the delay among the sub-modules and the delay in the sub-module
33
.
Budgeting is the conventional method for solving this problem. In this conventional method, the maximum value of the delay in the sub-module of each path is allocated in advance, and each sub-module satisfies the allocated delay restriction so as to determine the layout in a sub-module without considering the delay of the other modules.
However, since a delay occurring in a sub-module is greatly influenced by the layout, a tolerable delay cannot be estimated until the layout is determined, thereby making it difficult to determine budgeting. To solve this problem, the delay in the other modules should be estimated as a large value, but if this is done, the maximum value of the delay allowable in the sub-modules becomes small, making it difficult to determine the layout that satisfies the delay restriction in the module.
Thus, in the conventional layering design method, there was such a difficult problem that it was difficult to appropriately estimate the delay in a sub-module and to determine an overall layout with high efficiency.
SUMMARY OF THE INVENTION
The purpose of this invention is to efficiently implement a layout design of semiconductor integrated circuits.
The layout instrument for semiconductor integrated circuits in the first embodiment of this invention consists of a provisional layout unit that performs a provisional layout of cells in sub-modules of a semiconductor integrated circuit, a sub-module layout unit that implements a layout and wiring among sub-modules, and a provisional layout correction unit that corrects a provisional layout of cells in sub-modules when the delay determined by the layout and wiring implemented by the sub-module layout unit does not satisfy a specified delay restriction.
After a provisional layout of cells in sub-modules is implemented, the layout and wiring among sub-modules are carried out. If the delay determined thereby does not satisfy a specified delay restriction, the provisional layout of the cells in the sub-modules is corrected, and then the layout and wiring among the sub-modules are implemented again. Therefore, if this invention is used, it is possible to enhance the efficiency for carrying out a layout design without having to do such an unnecessary thing, after an entire layout has been determined, that the layout and wiring are implemented again because some delay does not satisfy the delay restriction in the sub-modules.
The provisional layout unit or the provisional layout correction unit may set the weight of the net that connects the cells to a value corresponding to the delay restriction when implementing a provisional layout of cells in the sub-modules.
By configuring these units as described above, the net is weighted so as to satisfy the delay restriction, and a provisional layout of the cells is determined based on the weight of the net, so it is possible to lay out the cells in the sub-modules so as to satisfy the delay restriction.
The provisional layout correction unit may increase the weight of the net that cannot easily satisfy the delay restriction when correcting the provisional layout of the cells in the sub-modules. By configuring this unit as described above, the length of the wire for the net that cannot easily satisfy the delay restriction can be shortened, so it is possible to efficiently determine the layout of the cells in the sub-modules.
The provisional layout unit may set the weight of the net among the flip-flops connected to external terminals to a value corresponding to the delay restriction. By configuring this unit as described above, the length of the wire among the flip-flops that input signals from external terminals and output signals to external terminals can be shortened, and the delay restriction can be satisfied.
The provisional layout unit may make a virtual net that connects input and output terminals of the cells having a delay restriction in the sub-modules, and may provisionally lay out the cells based on the virtual net list including the virtual net. Since it is not necessary to determine the layout of all the cells in the sub-modules when performing a provisional layout of the cells in the sub-modules, the time required to determine the layout that satisfies the delay restriction can be shortened by configuring the provisional layout unit as described above.
If there exist a plurality of sub-modules that have the same logic, but have a different delay restriction, the provisional layout unit may make a virtual module that sets the severest delay restriction of all the delay restrictions of all the sub-modules, and lay out the interior of the virtual module, and then the sub-module layout unit may replace a plurality of sub-modules with the virtual module and perform the layout and wiring among the sub-modules.
By conf
Fujitsu Limited
Lam Tuan T.
Nguyen Hiep
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