Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-02-13
2001-07-17
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C365S218000
Reexamination Certificate
active
06263477
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus and method of generating layout information, and, more particularly, to a layout information generating apparatus and method which generate information for writing ROM (Read Only Memory) codes and a mask option in a semiconductor integrated circuit incorporating a mask ROM.
2. Description of the Related Art
The background of the present invention will be discussed prior to a discussion of the related art.
FIG. 1
is a diagram showing the structure for one bit of a 32-word ROM. Referring to
FIG. 1
, first, a description will be given of the structure of a ROM layout section which is the premise of the art relating to a layout information generating apparatus.
With reference to
FIG. 1
, of an address signal of five bits A
0
to A
4
, A
0
and A
1
are input to an X decoder
32
to select one of select signal line X
0
to X
3
in the X-coordinate direction. Likewise, A
2
to A
4
in the 5-bit address signal A
0
-A
4
are input to an Y decoder
31
to select one of select signal lines Y
0
to Y
7
in the Y-coordinate direction. A ROM is constructed by laying out cell blocks
33
at the intersections of the thus constituted select signal lines in the X-coordinate direction and the Y-coordinate direction to set ROM cells, and leading out the existence
on-existence of each cell block
33
or ROM cell as a bit output B
0
.
In this case, whether the cell block
33
is laid out when a logic value is “1” or when it is “0” is determined by the circuit structure and the fabrication process. In the following description, it is assumed that the cell block
33
is laid out when a logic value is “1” and it is not when the logic value is “0.” It is “ROM data” that is the original data of this layout and that has a sequence of “0” and “1” (for the length of the address). The ROM data is generally expressed by a hexadecimal (16) notation from the viewpoint of management.
A description will now be given of the structure of a mask option which is the premise of the art relating to a layout information generating apparatus. The “mask option” is an option which is the other portion than the ROM and which can be selected by a user. The mask option includes an option for whether or not a pull-up resistor is present, switching between pull-up and pull-down, etc. While this portion is intrinsically irrelevant to ROM data, the set value of the mask option is designated, together with input ROM data, in the case of a ROM-incorporated microcomputer product.
FIG. 2
is a diagram exemplifying the circuit structure of a part of a chip with a designated mask option portion. Referring to
FIG. 2
, a pull-up resistor
21
is preset, and it is determined if the pull-up resistor
21
should be reflected on the circuit, depending on whether or not a cell (hereinafter called “dummy cell”)
22
is to be generated.
When the presence of the pull-up resistor is designated by a mask option designation field in an input ROM code, the dummy cell
22
is laid out and the pull-up resistor is reflected on the circuit as shown in FIG.
3
. In the case of no pull-up resistor, the dummy cell
22
is not laid out and the pull-up resistor is not reflected on the circuit as shown in FIG.
4
.
A description will now be given of the structure of a ROM definition and a mask option definition which are the premise of the art relating to a layout information generating apparatus.
Laying out ROM cells and dummy cells for the mask option in accordance with ROM data previously requires the position and coordinate information of the ROM cells and mask option dummy cells for an input address.
In the case of the ROM structure which has been discussed referring to
FIG. 1
, the position (select signal line) and coordinate information of ROM cells with respect to an input from the input address A
0
-A
4
as shown in, for example, FIG.
5
.
The correlation shown in
FIG. 5
is called a ROM definition which needs records by the number of ROM cells (one record consists of an address value and position information (select signal)). The memory capacity therefore becomes larger in proportion to the size of the ROM.
To reduce the memory capacity, an attempt has been made to compress a ROM definition by expressing the ROM definition in an array form by extracting and grouping ROM cells whose coordinate pitches and address pitches between adjoining ROM cells are identical.
Suppose that there is a ROM group consisting of 32 ROM cells as shown in FIG.
6
. The numerals in the individual cells in the diagram are addresses associated with the ROM cells.
FIG. 7
illustrates the compression of a ROM definition in consideration of adjoining ROM cells. The ROM definition, which should originally need a total of 32 ROM cell records, is compressed to the size of three records. Referring to
FIG. 7
, the ROM definition consists of the definition of a reference point, the definition of the first array and the definition of the second array. The definition information of the reference point consists of the coordinates and address of the reference point and a bit, the first array definition includes level information (
0
), the direction (X direction), the pitch (X_p), the number (
4
), the address pitch (
1
) and the X-directional array, and the second array definition includes level information (
1
), the direction (Y direction), the pitch (Y_p), the number (
8
), the address pitch (
4
) and the Y-directional array.
In the actual layout, the contents of those definitions are used directly or after development.
Likewise, a mask option requires an associated address and the position and coordinate information of dummy cells, which are called a mask option definition. Since its correlation table and the like are the same as those for the ROM definition, their description will be omitted.
On the premise that the above-described related art is understood, first prior art will be discussed below.
FIG. 8
is a block diagram showing the structure of the first prior art, and
FIG. 9
is a flowchart for explaining a process sequence according to the first prior art. Referring to
FIG. 8
, this conventional apparatus comprises a PROM (Programmable ROM) reader
1
, a ROM code input controller
2
, a screen display controller
3
, a display
4
, a data processor
5
, a layout information storage
6
, a keyboard controller
7
and a keyboard
8
.
The operation of the first prior art will be described with reference to the block diagram of
FIG. 8
, the flowchart of
FIG. 9
, the structural diagram for one bit of a ROM in FIG.
1
and the structural diagram of the pull-up resistor portion of a mask option in FIG.
2
.
To begin with, assuming that all the ROM cells are laid out and all the dummy cells of a mask option are laid out, a designer analyzes the design of the circuits to be laid out and the layout pattern. With regard to the ROM section, the arrangement of the X decoder and Y decoder is analyzed for each bit output, and the address of each ROM cell and bit arrangement information are extracted as address signal values (step S
301
), as shown in FIG.
10
.
Next, layout coordinate information is extracted based on the layout coordinates (X, Y) of a reference point
34
(see
FIG. 1
) as the reference point of one of ROM cells on the layout pattern, and the relative positional relationship among the individual ROM cells, which shows the distance from the reference point
34
computed from a pitch
35
(Y
P
) and a pitch
36
(X
P
) between ROM cells and the layout number, as shown in
FIG. 11
, (step S
302
). For example, information is extracted which indicates that a select signal line Y
1
is selected when A
4
and A
3
in the address signal A
4
-A
0
are 0 and A
2
is 1, and the Y coordinate of the ROM cell selected by this signal line Y
1
is Y+Y
P
.
Subsequently, the designer associates the address bit arrangement information with coordinate information on the layout pattern for each ROM cell to prepare a table indicating bit outputs as shown in
FIG. 12
, and
Do Thuan
Foley & Lardner
NEC Corporation
Smith Matthew
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