Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Bipolar transistor
Reexamination Certificate
2007-06-14
2010-11-09
Monbleau, Davienne (Department: 2893)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Bipolar transistor
C257S197000, C257SE29033
Reexamination Certificate
active
07829917
ABSTRACT:
The present invention provides a layout for a self-aligned semiconductor device, comprising an emitter mesa structure having an emitter electrode, and a base region that is comprised of a base electrode, with the base electrode deposited along crystal planes of the emitter mesa structure that undercut when the emitter mesa structure is etched, while avoiding depositing of the base electrode along crystal planes of the emitter mesa structure that do not undercut when the emitter mesa structure is etched. This allows the emitter electrode and the base electrode to self-align along the crystal planes that the emitter mesa structure undercuts when etched, and be isolated along the crystal planes that the emitter mesa structure does not undercut when etched. The present invention further provides dual interconnects mechanism and for connecting external circuitry to various semiconductor layers.
REFERENCES:
patent: 5063427 (1991-11-01), Tully et al.
patent: 5206524 (1993-04-01), Chen et al.
patent: 5345097 (1994-09-01), Nakagawa
patent: 5389554 (1995-02-01), Liu et al.
patent: 5468659 (1995-11-01), Hafizi et al.
patent: 5614423 (1997-03-01), Matsuoka et al.
patent: 5717228 (1998-02-01), Matsuoka et al.
patent: 6566693 (2003-05-01), Thomas et al.
patent: 00562272 (1993-09-01), None
patent: 50136159 (1975-10-01), None
patent: 4096274 (1992-03-01), None
patent: 5048078 (1993-02-01), None
Yataka Murata, et al., “IC-Oriented Self-Aligned High-Performance AlGaAs/GaAs Ballistic Collection Transistors and Their Applications to High-Speed ICs,” IEICE Trans. Electron, Sep. 1993, vol. E76-C, No. 9, pp. 1392-1401.
Hiroshi Masuda, et al., “Novel Self-Aligned Submicron Emitter InP/InGaAs HBT's Using T-Shaped Emitter Electrode,” IEEE, May 1995, pp. 643-647.
Shoji Yamahata, et al., “Over-220-Ghz-f, and fmax InP/InGaAs Double-Heterojunction Bipolar Transistors with a New Hexagonal-Shaped Emitter,” IEEE, 1995, pp. 163-166.
Sadao Adachi, et al., “Chemical Etching Characteristics of (001) InP,” J. Electrochem. Soc.: Solid-State Science and Technology, vol. 128, No. 6, (Jun. 1981), pp. 1342-1349.
S. Yamahata, et al., “Advanced InP/InGaAs HBT Technology for Low-Power Lightwave Communication Circuit Applications,” 2000 GaAs MANTECH Conference, pp. 37-40.
S. Noor Mohammand, et al., “Fundamentals, performance and reliability of III-V compound semiconductor heterojunction bipolar transistors,” University of Illinois at Urbana—Champaign Materials Research Laboratory & Coordinated Science Laboratory.
HRL Laboratories LLC
Monbleau Davienne
Reames Matthew
Tope-McKay & Assoc.
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