Layout for DUT arrays used in semiconductor wafer testing

Details Layout for DUT arrays used in semiconductor wafer testing Layout for DUT arrays used in semiconductor wafer testing

2005-10-03

2009-02-10

Nguyen, Ha Tran T (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C438S018000

Reexamination Certificate

active

07489151

ABSTRACT:
A layout for devices under test formed on a semiconductor wafer for use in wafer testing includes a first array of devices under test and a first pad set formed adjacent to the first array. The first pad set includes a gate force pad, a source pad, and a drain pad. Each of the devices under test in the first array is connected to the gate pad of the first pad set. Each of the devices under test in the first array is connected to the source pad of the first pad set. Each of the devices under test in the first array is connected to the drain pad of the first pad set.

REFERENCES:
patent: 5485095 (1996-01-01), Bertsch et al.
patent: 6844751 (2005-01-01), Marshall et al.
patent: 6873173 (2005-03-01), Kollmer et al.
patent: 6937047 (2005-08-01), Tran et al.
patent: 7253093 (2007-08-01), Lin et al.
patent: 7265034 (2007-09-01), Lu et al.
patent: 7332921 (2008-02-01), Nulty et al.
patent: 7378290 (2008-05-01), Cowles et al.
Ohkawa, S. et al. (2003). “Analysis and Characterization of Device Variations in an LSI Chip Using an Integrated Device Matrix Array,”Proceedings of International Conference on Microelectronic Test Structures, pp. 70-75.
Lefferts, R. et al. (2003). “An Integrated Test Chip for the Complete Characterization and Monitoring of a 0.25um CMOS Technology that Fits into Five Scribe Line Structures 150um by 5,000um,”Proceedings of International Conference on Microelectronic Test Structures, pp. 59-63.
Quarantelli, M. et al. (2003). “Characterization and Modeling of MOSFET Mismatch of a Deep Submicron Technology,”Proceedings of International Conference on Microelectronic Test Structures, pp. 238-243.
Saxena, S. et al. (Mar. 2004). “test Structures and Analysis Techniques for Estimation of the Impact of Layout on MOSFET Performance and Variability,”Proceedings of International Conference on Microelectronic Test Structures17:263-266.
Einfeld, J. et al. (Mar. 2004). “A New Test Circuit for the Matching Characterization of npn Bipolar Transistors,”Proceedings of International Conference on Microelectronic Test Structures17:127-131.
Yeric, G. et al. (2005). “Infrastructure for Successful BEOL Yield Ramp, Transfer to Manufacturing, and DFM Characterization at 65 nm and Below,”Proceedings of IEEE Design&Test of Computers, pp. 232-239.
Schaper, U. et al. (Apr. 2005). “Parameter Variation on Chip Level,”Proceedings of International Conference on Microelectronic Test Structures18:155-158.

Affiliated with

Also associated with

Rating

Layout for DUT arrays used in semiconductor wafer testing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Layout for DUT arrays used in semiconductor wafer testing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Layout for DUT arrays used in semiconductor wafer testing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4135126