Layout for distributed sense amplifier driver in memory device

Details Layout for distributed sense amplifier driver in memory device Layout for distributed sense amplifier driver in memory device

2008-07-22

2008-07-22

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230030, C365S230080, C365S185110, C365S189080

Reexamination Certificate

active

07403443

ABSTRACT:
A semiconductor memory device is disclosed having a layout including, alternating pluralities of memory cell arrays and word line driving blocks arranged next to alternating pluralities of sense amplifier blocks and conjunction blocks, such that each sense amplifier block is located lateral to a corresponding memory cell array, and each conjunction block is located lateral to a corresponding word line driving block. Each sense amplifier block alternately includes one of a supply voltage driver and a ground voltage driver.

REFERENCES:
patent: 7184347 (2007-02-01), Lee et al.
patent: 7336518 (2008-02-01), Chang et al.
patent: 06-176571 (1994-06-01), None
patent: 11-328951 (1999-11-01), None
patent: 2000-124415 (2000-04-01), None
patent: 2001-093276 (2001-04-01), None
patent: 100200760 (1999-03-01), None

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