Layout for data storage circuit using shared bit line and method

Details Layout for data storage circuit using shared bit line and method Layout for data storage circuit using shared bit line and method

1998-02-04

2000-02-01

Yoo, Do Hyun

Static information storage and retrieval

Systems using particular element

Capacitors

365 63, 365174, 365190, G11C 700

Patent

active

060210648

ABSTRACT:
An integrated circuit includes a memory array implemented with as few as two transistors, and four access lines per cell. The array includes row lines and bit lines, with the internally-arranged bit lines shared by adjacent cells. According to one embodiment, each memory cell is accessed in response to levels established on selected ones of the row and bit lines, and two adjacent memory cells are located on either side of one of the bit lines. This bit line interconnects a first MOS-based transistor in one of the two memory cells and a second MOS-based transistor in the other of the two memory cells. Other aspects of the invention are directed to advantages concerning the laying out of interconnects used in each memory cell. For example, the first MOS-based transistor can have its drain connected to the drain of the second MOS-based transistor using an interconnecting layer arranged substantially at a right angle relative to the first direction or at an acute angle relative to the first direction.

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