Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1997-03-04
2001-02-27
Lintz, Paul R. (Department: 2768)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C703S016000
Reexamination Certificate
active
06195787
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of designing the layout of a semiconductor integrated circuit.
2. Prior Art
Recently, various excellent CAD (Computer Aided Design) tools using computer technology have been developed. These CAD tools are now used to carry out almost all required operations in developing semiconductor integrated circuits, such as logic designing and layout designing. In recent years, however, a CAD tool merely capable of automatic designing has not been deemed satisfactory, and there is an increasing demand been for a CAD tool capable of high-quality automatic designing. In particular, the electric performance of the resulting semiconductor integrated circuit devices such as operating speed and power consumption depends on whether layout designing is good or not, and therefore numerous proposals have been made for ensuring the high quality of the final product at the stage of layout designing.
FIG. 2
shows a flowchart of automatic designing carried out by an automatic designing system proposed under the above circumstances. In designing a semiconductor integrated circuit by using this system, a designer prepares function descriptive information and information related to constraint conditions (steps S
1
and S
2
). The function descriptive information consists of information defining the circuit structure of a semiconductor integrated circuit to be designed, more specifically a list describing what macro (the kind or type of a standard part such as a NAND gate and a NOR gate) is to be used for each circuit element of the circuit, and how the wiring is to be provided between the circuit element and another circuit element. The information related to constraint conditions consists of information describing conditions required for setting the operating timing of circuit elements of the semiconductor integrated circuit to be designed to desired timing. For example, in the case where there is a critical path which requires setting the propagation delay time of a signal transmitted therethrough within a predetermined range, the constraint conditions include component elements on the critical path and the range of the propagation delay time.
The function descriptive information and the constraint condition information thus prepared are delivered to a CAD tool. In the CAD tool, there are previously stored various kinds of libraries needed for automatic designing of semiconductor integrated circuits, including a logic simulation library defining the contents of a logic calculation to be performed by each macro, and a layout library defining artwork information (related to dimensions and shapes of patterns, for example) associated with transistors constituting the respective macros, wiring patterns and others. The CAD tool refers to these various libraries to thereby start automatic designing according to the function descriptive information and the constraint condition information prepared by the designer.
First, a processing called “logic synthesization” is carried out at a step S
3
. This processing prepares by logic synthesization a file defining the structure of a circuit to be designed by the automatic designing as a logic circuit, based on the function descriptive information, constraint condition information and logic simulation library.
Then, a logic simulation is carried out using the thus obtained file and a test pattern (time series signal pattern defining an input waveform applied to the circuit, and a response waveform to be obtained from the circuit when the input waveform is applied) that is used for confirming the function, to determine whether or not the circuit defined by the function descriptive information exhibits the intended logical function (step S
4
).
When no abnormality is found in the logical function exhibited by the circuit as a result of the logic simulation, the procedure proceeds to a layout processing at a step S
5
. The layout processing is roughly divided into two processings. In the first processing, a cell (hereinafter referred to as an artwork cell) including transistors, wiring pattern and others, which corresponds to each of the macros appearing in the function descriptive information, is virtually positioned or arranged in a chip. The artwork cell corresponding to each macro is prepared using the artwork information in the layout library which corresponds to the relevant macro. If a critical path is designated as a constraint condition, an artwork cell corresponding to each component element on the critical path is preferentially positioned, and after completion of the positioning, other artwork cells with a lower priority are positioned. In the second processing, the wiring pattern, such as a pattern of signal wires connecting the respective art work cells virtually positioned in the chip, feeder wires for supplying electric power and earthing wires, is produced. The wiring pattern for the signal wires is automatically produced according to the above-described function descriptive information.
After completion of the layout processing, a power consumption simulation is carried out at a step S
6
. Specifically, resistance values of the feeder wires and earthing wires produced by the layout processing are determined, consumption current values of component elements constituting the semiconductor integrated circuit are calculated, and it is determined based on the obtained resistance values and consumption current values whether or not the consumption current can be reliably allowed to flow into each of the feeder wires and earthing wires.
For example, a result of the layout processing is shown in FIG.
3
. In this example, elements M
1
and M
2
are connected to an earthing wire L
1
, and elements M
3
, M
4
, and M
5
are connected to an earthing wire L
2
and consumption currents I
1
to I
5
flow through the earthing wire L
1
or L
2
to a bonding pad for an earthing terminal. The consumption power simulation calculates the consumption currents I
1
to I
5
. As a result, if it is determined that the total consumption current flowing through the earthing wire L
2
is excessive such that electromigration can occur, the procedure returns to a previous processing such as the layout processing or the logic simulation to carry out a redesign. On the other hand, if the calculated consumption current value flowing through each earthing wire falls within a tolerance range determined based on the wire width, etc., the result of the layout processing is adopted as it is, that is, a mask is produced based on the layout result, and an engineering sample (ES) of the semiconductor integrated circuit is experimentally manufactured (step S
7
). Then, electrical properties of the obtained ES are evaluated. If the evaluation results are found satisfactory, the development is completed, whereas if they are not satisfactory, a redesign of the semiconductor integrated circuit is carried out.
According to the above described conventional automatic designing system, by previously setting constraint conditions, it is possible to carry out a layout design which takes into consideration the operating timing of circuit elements of the semiconductor integrated circuit, such as presence of a critical path. The magnitude of current flowing to each circuit element of a semiconductor integrated circuit, however, cannot be determined until after the layout of circuit elements constituting the circuit and the wiring system connecting them are fixed, and therefore the reliability of the current magnitude is confirmed after completion of the layout designing as stated above. This, however, can often necessitate redesigning of the layout, leading to an increased developing cost. Further, although in the case of a semiconductor integrated circuit where the consumption current of each circuit element can be grasped beforehand, a countermeasure such as redesigning of the layout can be taken before trial manufacture of ES, it is actually very difficult in the case of a LSI to determine beforehand the consumption
Garbowski Leigh Marie
Lintz Paul R.
Pillsbury Madison & Sutro LLP
Yamaha Corporation
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