Layout design system, layout design method and layout design...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000

Reexamination Certificate

active

07013444

ABSTRACT:
A layout design system of a semiconductor integrated circuit, comprising: a library information storage unit configured to register a basic via shape list; a technology database storage unit configured to register a list expressing an optimum wire terminating process for each via shape of said basic via shape list registered in said library information storage unit; and a central processing control unit configured to refer to the lists respectively registered in said library information storage unit and said technology database storage unit, select an optimum line processing, and execute a line design.

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patent: 6813756 (2004-11-01), Igarashi et al.
patent: 3-237741 (1991-10-01), None
patent: 6-332987 (1994-12-01), None
U.S. Appl. No. 09/713,050, filed Nov. 2000, Igarashi et al.

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