Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-04-12
2004-07-13
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06763508
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from prior Japanese Patent Application P2001-115780 filed on Apr. 13, 2001; the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a layout design system of semiconductor integrated circuits facilitating an automatic selection of a wiring pattern by use of CAD, and more particularly to a layout design system of semiconductor integrated circuits for designing a terminal layout of an oblique wiring pattern, a layout design method, and a layout design program. The present invention further relates to a manufacturing method of semiconductor integrated circuits using the layout design system, layout design method and layout design program.
2. Description of the Related Art
Progress of LSI technologies makes the circuit scale larger, and this causes an increase in an amount of logic design computations for the circuit. Accordingly, as a logic design method capable of effectively utilizing computers, a logic design by use of Computer Aided Design (CAD) has been carried out.
In designing interconnection of basic horizontal and vertical lines in the orthogonal coordinate system on CAD, horizontal and vertical lines often terminate at an intersection point of two or more orthogonal lines. When the horizontal lines and the vertical lines are formed in different levels in an actual semiconductor device, a via hole must be formed at the terminal portions of the metal lines to connect the horizontal and vertical lines three-dimensionally. As a matter of course, a connection pattern corresponding to the via hole must be defined at the terminal portions of the horizontal and vertical lines even in a layout by use of CAD.
Generally, if two basic orthogonal lines having an ordinary width W terminate at an intersection, wire terminating process is carried out to extend the ends of the orthogonal lines by W/2.
FIGS. 1A
to
1
E illustrate an example of the wire terminating process of the basic orthogonal lines of the minimum width. In
FIG. 1A
, a horizontal line
901
and a vertical line
903
intersect each other and terminate there. In a CAD system, only the intersection point at which the center lines
902
and
904
of the respective lines intersect each other is recognized as an intersection point
908
. The CAD system does not recognize the overlap of the two orthogonal lines at all.
When, in an actual semiconductor device, the horizontal line
901
is formed in a lower level and the vertical line
902
is formed in an upper level, these two lines must be connected three-dimensionally by use of a via hole. As a matter of course, the CAD layout requires a connection pattern
905
for connecting the two lines. The connection pattern
905
has a bottom metal
901
a
which is a part of the end portion of the line
901
in the lower level, a top metal
903
a
, which is a part of the end portion of the line
903
in the upper level, and an opening pattern (hereinafter, referred to as a “cut pattern” or simply as a “cut”)
907
for connecting the top and bottom metals
903
a
and
901
a.
In the example of
FIGS. 1A
to
1
E, since the CAD recognizes that the two lines intersect each other, it is possible to define the connection pattern
905
at the intersection point
908
on the layout. However, since an overlapped area where the horizontal and vertical lines
901
and
903
overlap is very small in the state of
FIG. 1A
, even when the via hole is formed based on the connection pattern
905
in the actual semiconductor integrated circuit, the connections of the upper and lower levels and the via hole cannot be achieved successfully.
To overcome this problem, in the design system of the semiconductor integrated circuits, the ends of the horizontal and vertical lines
901
and
903
are respectively extended by W/2, as shown in
FIG. 1B
, so that the two lines completely overlap at their end portions. Then, wire terminating process is carried out so as to place the connection pattern
905
on the overlapped area, as shown in FIG.
1
C.
FIG. 1D
illustrates the shape of the connection pattern
905
at the end portion of the basic orthogonal lines at which they intersect each other, when viewed from above. Since the connection pattern
905
is placed on the intersection of the basic orthogonal lines, the connection pattern
905
has a square shape when viewed from above.
FIG. 1E
is a side view of the shape of the connection pattern
905
. The lower metal
901
a
and the upper metal
903
a
are connected by the cut
907
.
FIG. 2
illustrates another example of wire terminating process of two orthogonal lines having wide widths. In this case, the two wider orthogonal lines intersect and terminate at the intersection point. These wider lines are special lines such as a power source line and a clock line, and subjected to a wire terminating process similarly to general signal lines. A connection pattern
915
is placed on an overlapped area where a wider horizontal line
911
and a wider vertical line
913
intersect. At this time, since the overlapped area is made wider, a plurality of cuts
917
are provided in one connection pattern. Also in this case, both of the horizontal and vertical lines
911
and
913
are extended by W/2, and a metal pattern completely including the connection pattern
915
having the plurality of cuts
917
is placed in the overlapped area.
It is easy for the CAD system to carry out the wire terminating process to design interconnection consisting of only basic orthogonal lines in the horizontal and vertical directions, as in the examples shown in
FIGS. 1 and 2
.
However, as the configuration of semiconductor integrated circuits is made finer, higher precision is required in every respect including a manufacturing process and components of a semiconductor integrated circuit. Particularly, a delay component caused by an interconnection (or a wiring) significantly affects the performance of the integrated circuit as the integrated circuit is made finer. Therefore, it is an important subject how to reduce such a delay in the integrated circuit.
Most of the delay components of the interconnection are caused by a line resistance. The most effective way to reduce the line resistance is to reduce a line length. Accordingly, it has been proposed to use oblique lines, in addition to the basic orthogonal lines extending in the horizontal and vertical directions, to reduce the distance between two points in a semiconductor circuit. There is also a proposal to design a circuit layout using oblique lines on CAD. In this case, as the lines including the oblique lines are made in the form of multi-level structure composed of a larger number of levels, for example, the shape and the forming process of via holes connecting basic orthogonal lines in a lower level and oblique lines in an upper level must be contrived.
The inventors of the present invention have proposed in U.S patent application Ser. No. 09/338,593 a technique for greatly reducing a line resistance of oblique lines itself. This is achieved by setting the width and film thickness of the oblique line to 2
1/2
times as large as those of the basic orthogonal lines. In this gazette, a technology for fully securing a cut area by contriving the shape of a via hole connecting metal lines of different levels is also proposed. In order to realize a high-speed operation of an integrated circuit, the inventors also proposed a tree-type clock supply line path comprised of a combination of oblique lines and the basic orthogonal lines.
FIG. 3
illustrates a line structure using the oblique lines. As shown in
FIG. 3
, considered is the line structure having a horizontal first-level metal line
921
, a vertical second-level metal line
922
, a horizontal third-level metal line
923
, an oblique fourth-level metal line
924
, and a fifth-level metal line
925
perpendicular to the fourth-level metal line
924
. When the first-level m
Igarashi Mutsunori
Mitsuhashi Takashi
Garbowski Leigh M.
Gray Cary Ware & Freidenrich LLP
Kabushiki Kaisha Toshiba
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