Layout design method for semiconductor integrated circuits

Details Layout design method for semiconductor integrated circuits Layout design method for semiconductor integrated circuits

2007-04-17

2007-04-17

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

11255965

ABSTRACT:
A method of designing a semiconductor integrated circuit creates a net list with cells from a low-threshold-voltage cell library, then arbitrarily replaces some or all of the cells with cells from a high-threshold-voltage cell library. A timing analysis is performed, and if necessary, the net list is further modified by using cells from the low-threshold-voltage cell library to eliminate or reduce timing errors. Place and route processes are then carried out to create layout data, and another timing analysis is performed. If timing errors are found, the paths on which the timing errors occur are optimized by resizing or replacing cells or inserting buffers until the timing errors are eliminated. This method maximizes usage of cells from the high-threshold-voltage cell library and therefore produces a design with reduced leakage current.

REFERENCES:
patent: 2004/0168143 (2004-08-01), Kishibe
patent: 09-246389 (1997-09-01), None
patent: 09-282341 (1997-10-01), None

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