Layout design method and system for an improved place and route

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

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716 10, G06F 1750

Patent

active

061102229

ABSTRACT:
A layout design method and system for a semiconductor integrated circuit improves circuit performances related to operated frequency and power consumption by improved placement and routing. The method features an intersecting wiring predicting step that predicts the number of the intersecting wirings based on predicted wiring routes and an intersecting wiring capacitance calculating step that calculates the capacitances between the intersecting wirings.

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