Layout design apparatus

Details Layout design apparatus Layout design apparatus

1997-04-28

2000-11-07

Lintz, Paul R.

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

716 10, G06F 1750

Patent

active

061451169

ABSTRACT:
A layout design apparatus for arranging circuit elements and routing the circuit elements to perform a layout design of a logical circuit, includes path delay analysis means for performing delay analysis processing on a layout result which is obtained by performing a layout design of a logical circuit with a predetermined method, relay buffer insertion means for performing a logical alteration of the logical circuit to reduce the delay error when a delay error exists in the layout result through the delay analysis processing, and incremental routing means for rerouting the layout result in accordance with the result of the logical alteration by the logical altering means.

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T. Aoki et al, "Fan-Out Restructuring Algorithm for Post-placement Timing Optimization", ASP-DAC '95 CHDL '95 VLSI '95, 1995, Aug. 8-Sep. 1, 1995, pp. 417-422, Chiba, Japan.

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