Layout configurable electrostatic discharge device for...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S361000, C257S355000, C257S173000, C257S175000

Reexamination Certificate

active

06707110

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an Electrostatic Discharge (ESD) protection device according to the preamble of the first claim.
BACKGROUND OF THE INVENTION
The more and more extensive use of smart power technology in demanding environments, such as automotive applications, requires appropriate and specific Electro Static Discharge (ESD) protection devices. Integrated circuits (IC) used for such harsh applications require a high ESD robustness and latch-up free operation and they have to operate at high operating temperatures and voltages.
FIG. 1
shows a current voltage curve of a typical prior art bipolar ESD device, having a breakdown voltage V
bd
of about 65V, a trigger voltage V
t
of about 95V and a holding voltage V
h
of about 40V.
To provide an effective ESD protection for the whole integrated circuit, on-chip ESD protection circuits are added to the input/output pads (I/O) (
1
) and supply pads (
7
) of the IC (
2
) (cf. FIG.
2
). The specifications of such on-chip ESD protection circuits such as triggering voltage and holding voltage are different for an Input/Output structure (I/O-port) and a power supply. In case of e.g. an I/O-port shown in
FIG. 2
a
, a voltage peak V
p
or discharge on the input bonding pad (
1
) transferred to the chip (
2
) must be limited in order to prevent damage of the input of subsequent devices and circuits (
2
). This requires an ESD device (
3
) that triggers and holds at a low voltage, avoiding a permanent overload of the circuit (
2
). The breakdown voltage V
bd
and trigger voltage V
t
such ESD device must be less than a specified maximum voltage V
max
. On the other hand a power supply line providing power from the supply pad (
7
) to the circuit (
2
), as shown in
FIG. 2
b
, must maintain a high enough voltage, to prevent unwanted switching off of a circuit due a voltage drop on this supply line. This requires an ESD device (
3
) with a breakdown voltage V
bd
and a holding voltage V
h
that are above a minimal voltage V
min
to maintain a specified minimal supply voltage. Table 1 summarises typical requirements for an ESD structure used in I/O and power supply of an integrated circuit to be used in automotive applications. The corresponding ESD protections are nowadays designed for each application or circuit.
From WO-A-99/21229, a self-triggered bipolar device is known which is used as ESD protection device in smart power technology. WO-A-99/21229 describes a lateral bipolar device used as an electrostatic discharge device. The collector of this bipolar device consists of a highly doped region and a lowly doped region adjacent to the base region. The voltage applied to the collector electrode at which this bipolar device triggers, depends on the width of this lowly doped collector region. In other words, the width of this lowly doped collector region is a layout parameter which can be predetermined for selecting a desired trigger voltage of the bipolar device. The holding voltage of the bipolar device is however substantially independent from this parameter.
AIM OF THE INVENTION
It is an aim of the present invention to provide an electrostatic discharge device of which the holding voltage can be predetermined.
SUMMARY OF THE INVENTION
For the purpose of clarity, the invention will be described in the following for an npn bipolar device. However, it should be apparent that the invention also relates to pnp bipolar devices.
The (npn) ESD protection device according to one aspect of the invention comprises a first highly p-doped region provided with a base contact, a first highly n-doped region provided with a collector contact and, in between, a second highly n-doped region provided with an emitter contact. The first highly doped p-doped region and the second highly n-doped region are applied or formed in a weakly p-doped region. This weakly p-doped region has a lateral overlap which extends towards the first highly n-doped region, the lateral overlap has a predetermined width “d”. The first highly n-doped region is applied in a weakly n-doped region. This weakly n-doped region and the weakly p-doped region are applied in a more weakly n-doped region. A highly n-doped buried layer (BLN) is located underneath the more weakly n-doped region and extends below at least a portion of the weakly n-doped region and at least a portion of the weakly p-doped region.
The first highly p-doped region has a doping concentration above that of the weakly p-doped region. The first highly n-doped region has a doping concentration above that of the weakly n-doped region, which in turn has a doping concentration above that of the weakly n-doped region. The highly n-doped buried layer (BLN) has a doping concentration above that of the weakly n-doped region. Because of its structure, the ESD device is provided for enabling a lateral current component from the first highly n-doped region in the direction of the second highly n-doped region and a vertical current component from the BLN in the direction of the second highly n-doped region.
In order to control the holding voltage of the ESD-device according to the invention, the layout parameter “d” is varied. It has been found that by varying the “d” parameter, it can be determined how electrical current will flow through the device in holding state, i.e. after the breakthrough voltage is reached and the device snaps back to the holding voltage. At smaller values of “d”, the current will flow more laterally, i.e. more near the surface of the device, than at larger values of “d”, at which the current will flow more vertically. In other words, for smaller values of “d” the lateral current component is favoured, whereas for larger values of “d” the vertical current component is favoured. Because of this possible selection between the vertical and the lateral current components, multiplied by the collector resistance of the device in the conductive state, the “d” parameter enables a selection in a range of obtainable holding voltages for the ESD device of the invention in the conductive state.
In the ESD device of the invention, the more weakly n-doped region separates the weakly n-doped region from the BLN. This means that a sinker region is omitted in the device of the invention. Such a sinker region is used in the prior art to connect the weakly n-doped region with the BLN and forms a reduction in the collector resistance of the device. However, this reduction in the collector resistance doesn't provide an adequate solution in the device of the invention, as this leads to a predominance of the vertical current component. The “d” parameter would have to be chosen so small in order to make the lateral current component dominant, that there would be substantially no lateral overlap of the weakly p-doped region left. The width of the overlap would have to be reduced to a physically unobtainable size. So if a sinker region were present, it would become substantially impossible to select a ration for the lateral and the vertical current components and as such substantially impossible to obtain a desired holding voltage of the device by choosing a value for “d”.
Furthermore, the implementation of a sinker region in an ESD device requires a full BiCMOS process. Omitting the sinker region has the economic advantage that the device of the invention can be produced in a simplified or reduced BiCMOS process, which makes it possible to reduce the number of patterning and implementation steps.
An advantage of the present invention is that it offers an ESD structure with which a desired holding voltage can be easily achieved by adapting the layout. As this can be achieved by changing only one layout parameter, this offers an easy, flexible and cost-effective solution.
Because of the above-described structure of the ESD device according to the invention, the device can be seen as comprising a lateral transistor and a vertical transistor. The lateral transistor enables the lateral current component and is formed by the sequence of the second highly n-doped region, the weakly p-doped regio

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