Layout architecture for improving circuit performance

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular power supply distribution means

Reexamination Certificate

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Details

C257S369000, C257S532000, C257S355000

Reexamination Certificate

active

07821039

ABSTRACT:
An integrated circuit structure includes an integrated circuit structure including a PMOS transistor including a first gate electrode; a first source region; and a first drain region; an NMOS transistor including a second gate electrode, wherein the first gate electrode and the second gate electrode are portions of a gate electrode strip; a second source region; and a second drain region. No additional transistors are formed between the PMOS transistor and the NMOS transistor. The integrated circuit further includes a VDD power rail connected to the first source region; a VSS power rail connected to the second source region; and an interconnection port electrically connected to the gate electrode strip. The interconnection port is on an outer side of a MOS pair region including the PMOS transistor, the NMOS transistor, and the region between the PMOS transistor and the NMOS transistor. The portion of the gate electrode strip in the MOS pair region is substantially straight.

REFERENCES:
patent: 4319342 (1982-03-01), Scheuerlein
patent: 4682201 (1987-07-01), Lipp
patent: 5019889 (1991-05-01), Shintani et al.
patent: 6242767 (2001-06-01), How et al.
patent: 7219324 (2007-05-01), Sherlekar et al.
patent: 7603634 (2009-10-01), Sluss et al.

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