Layout and wiring system and recording medium recording the...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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Details

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07032205

ABSTRACT:
It is determined whether a short-run rule can be adapted into a position, where a via cell is parallel and adjacent to a portion of wiring or another via cell. The via cell and the portion of the wiring is arrayed at the smallest space in the wiring. When determined that the short-run rule can be adapted thereinto, via cell data is created. The via cell data includes a via margin which is so reduced in size that the via margin can be equal to or larger than the wiring minimum space. With the created via cell data, automatic layout and wiring is performed. The via cell data is replaced with art-work data including a via cell with an original via margin, so as to be output.

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patent: 01-302856 (1989-12-01), None
patent: 3-029343 (1991-02-01), None
patent: 10-294373 (1998-11-01), None

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