Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-06-07
2001-04-17
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S488000, C438S248000, C438S386000
Reexamination Certificate
active
06218696
ABSTRACT:
BACKGROUND
1. Technical Field
This disclosure relates to semiconductor layouts and more particularly, to a layout for semiconductor memory cells with vertical transistors.
2. Description of the Related Art
In semiconductor memory devices, gate conductors are formed through a memory array to activate access transistors for reading and writing to storage nodes disposed in deep trenches by charging or discharging the storage node. In prior art systems, access transistors are disposed on a surface of the chip and require a large amount of chip area. These memory cells with planar transistors are activated by a line conductor that forms a gate conductor for the planar transistor. The line width of this gate conductor was critical for these prior art memory cell designs since the line width also defined the gate length for the transistor.
Since the gate conductor (GC) typically has a high electrical resistance (it is generally formed from polysilicon and tungsten silicide), methods were implemented to improve usage of the gate conductor due to it high resistance. One way to address the high resistance of the gate conductor is to form a stitched or bridged pattern. The stitched pattern includes alternating the gate conductors between metal layers to bring the line resistance to a lower level. This reduces the line resistance to a tenth of the gate conductor value.
With the transition to vertical transistors to reduce layout area for memory cells, the gate conductor layer is only used for wiring purposes, and the gate conductor is no longer used to define the gate length. Therefore, the gate conductor width is no longer critical.
Therefore, a need exists for improved layouts and wiring schemes which take advantage of the gate conductor orientation for vertical transistors.
SUMMARY OF THE INVENTION
A memory device having vertical transistors in accordance with the present invention includes an active area pad isolated from adjacent active area pads on all sides, and having a set of trench capacitors associated therewith. The set of trench capacitors are coupled to the active area pad through vertical transistors. The active area pad is configured to connect the set of trench capacitors to a first contact. A gate conductor pad is disposed between a set of active area pads and adapted to activate at least one vertical transistor in each active area pad adjacent to the gate conductor pad. Each gate conductor pad is activated by a second contact such that when the gate conductor pad is activated through the second contact the at least one vertical transistor in each active area pad conducts to provide access to the trench capacitors and the active area pad transfers a state between the first contact and the trench capacitors.
A semiconductor memory having vertical access transistors includes a substantially square active area pad having a trench capacitor formed at each corner of the active area pad. The trench capacitors are coupled to the active area pad through vertical transistors. The active area pad is configured to connect the set of trench capacitors to a first contact when the vertical transistors are conducting. A substantially square gate conductor pad is disposed between four active area pads such that corners of the gate conductor pad overlap adjacent corners of the four active area pads. The gate conductor pad is adapted to activate one vertical transistor corresponding to the corner of each active area pad overlapped by the gate conductor pad. The gate conductor pad is activated by a second contact such that when the gate conductor pad is activated through the second contact, the one vertical transistor in each active area pad conducts to provide access to the trench capacitors and to transfer a state between the first contact and the trench capacitors.
Another semiconductor memory having vertical access transistors includes a plurality of substantially square active area pads. Each active area pad has a trench capacitor formed at each corner of the active area pad. The trench capacitors are coupled to the active area pad through vertical transistors. The active area pads are configured to connect the set of trench capacitors to a first contact when the vertical transistors are conducting. A plurality of substantially square gate conductor pads, each is disposed between four active area pads to form a checkerboard pattern between the gate conductor pads and the active area pads. Each of the gate conductor pads has corners overlapping adjacent corners of the four active area pads. Each corner of the gate conductor pad is adapted to activate one vertical transistor corresponding to the corner of each active area pad overlapped by the gate conductor pad. Each gate conductor pad is activated by a second contact such that when the gate conductor pad is activated through the second contact the one vertical transistor in each active area pad conducts to provide access to the trench capacitors and to transfer a state between the first contact and the trench capacitors. A first metal layer is connected to the first contacts, and a second metal layer is vertically spaced apart from the first metal layer. The second metal layer is connected to the second contacts for activating the gate conductor pads.
In alternate embodiments, the active area pads and the gate conductor pad may be one of square, circular and triangular in shape. The first contact preferably connects to a first metallization layer, and the second contact preferably connects to a second metallization layer. The first metallization layer preferably includes first metal lines, and the second metallization layer preferably includes second metal lines wherein the first metal lines and the second metal lines have a substantially equal pitch and are disposed in a zig-zag pattern. The active area pads and the gate conductor pads may be disposed in a checkerboard pattern. The first contact may be connected to a bitline and the second contact may be connected to a wordline. The device or memory is divisible into memory cells such that the memory cells may have an area of about 4F
2
or about 6F
2
.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
REFERENCES:
patent: 6091094 (2000-07-01), Rupp
patent: 6093614 (2000-07-01), Gruening et al.
Chaudhuri Olik
Infineon Technologies North America Corp.
Peralta Ginette
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