Layout and process to contact sub-lithographic structures

Details Layout and process to contact sub-lithographic structures Layout and process to contact sub-lithographic structures

2008-04-01

2008-04-01

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S694000, C438S717000, C257S048000, C257SE21038, C257SE21039, C257SE21314

Reexamination Certificate

active

07351666

ABSTRACT:
An integrated circuit and method for fabrication includes first and second structures, each including a set of sub-lithographic lines, and contact landing segments connected to at least one of the sub-lithographic lines at an end portion. The first and second structures are nested such that the sub-lithographic lines are disposed in a parallel manner within a width, and the contact landing segments of the first structure are disposed on an opposite side of a length of the sub-lithographic lines relative to the contact landing segments of the second structure. The contact landing segments for the first and second structures are included within the width dimension, wherein the width includes a dimension four times a minimum feature size achievable by lithography.

REFERENCES:
patent: 6767693 (2004-07-01), Okoroanyanwu
patent: 6875703 (2005-04-01), Furukawa et al.
patent: 2004/0211953 (2004-10-01), Khouri et al.
patent: 2006/0189045 (2006-08-01), Shum et al.

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