Fishing – trapping – and vermin destroying
Patent
1995-04-10
1997-07-29
Bowers, Jr., Charles L.
Fishing, trapping, and vermin destroying
437233, 437101, 437976, 148DIG122, H01L 2120, H01L 213205
Patent
active
056521561
ABSTRACT:
A method of forming a multilayered polysilicon gate which inhibits penetration of ions through the polysilicon gate to the underlying gate oxide layer is described. A gate silicon oxide layer is formed over the surface of a semiconductor substrate. A layer of amorphous silicon is grown overlying the gate silicon oxide layer. A layer of polysilicon is grown over the amorphous silicon layer wherein silicon grain boundaries of the polysilicon layer are misaligned with silicon grain boundaries of the amorphous silicon layer. The amorphous silicon and the polysilicon layers are etched away where they are not covered by a mask to form the multilayered polysilicon gate. The mismatched silicon grain boundaries of the multilayered polysilicon gate inhibit ions from penetrating through the polysilicon gate to the underlying gate oxide layer.
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Translation of JP 2-224223 Sep. 1990.
S. Wolf & R.N. Tauber "Silicon Processing For the VLSI Era" vol. I, 1986, pp. 175-181, 198, 290-295, 325.
Jiaw-Ren Shih
Liao Siu-han
Bowers Jr. Charles L.
Pike Rosemary L. S.
Radomsky Leon
Saile George O.
Taiwan Semiconductor Manufacturing Company , Ltd.
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