Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction
Reexamination Certificate
2008-09-23
2008-09-23
Pham, Thanhha (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Heterojunction
C257S065000, C257SE31036
Reexamination Certificate
active
10948421
ABSTRACT:
A method for forming strained Si or SiGe on relaxed SiGe on insulator (SGOI) or a SiGe on Si heterostructure is described incorporating growing epitaxial Si1−yGeylayers on a semiconductor substrate, smoothing surfaces by Chemo-Mechanical Polishing, bonding two substrates together via thermal treatments and transferring the SiGe layer from one substrate to the other via highly selective etching using SiGe itself as the etch-stop. The transferred SiGe layer may have its upper surface smoothed by CMP for epitaxial deposition of relaxed Si1−yGey, and strained Si1−yGeydepending upon composition, strained Si, strained SiC, strained Ge, strained GeC, and strained Si1−yGeyC or a heavily doped layer to make electrical contacts for the SiGe/Si heterojunction diodes.
REFERENCES:
patent: 4826787 (1989-05-01), Muto et al.
patent: 5013681 (1991-05-01), Godbey et al.
patent: 5240876 (1993-08-01), Gaul et al.
patent: 5298452 (1994-03-01), Meyerson
patent: 5387555 (1995-02-01), Linn et al.
patent: 5462883 (1995-10-01), Dennard et al.
patent: 5476813 (1995-12-01), Naruse
patent: 5569620 (1996-10-01), Linn et al.
patent: 5650353 (1997-07-01), Yoshizwa et al.
patent: 5659187 (1997-08-01), Legoues et al.
patent: 5906951 (1999-05-01), Chu et al.
patent: 6059895 (2000-05-01), Chu et al.
patent: 6103597 (2000-08-01), Aspar et al.
patent: 6118181 (2000-09-01), Merchant et al.
patent: 6153495 (2000-11-01), Kub et al.
patent: 6255731 (2001-07-01), Ohmi et al.
patent: 6323108 (2001-11-01), Kub et al.
patent: 6328796 (2001-12-01), Kub et al.
patent: 6521041 (2003-02-01), Wu et al.
patent: 6524935 (2003-02-01), Canaperi et al.
patent: 6573126 (2003-06-01), Cheng et al.
patent: 6689211 (2004-02-01), Wu et al.
patent: 2002/0072130 (2002-06-01), Cheng et al.
patent: 515453 (1993-02-01), None
patent: 758304 (1995-03-01), None
patent: 9180999 (1997-07-01), None
patent: 10308503 (1998-11-01), None
patent: 11-233771 (1999-08-01), None
patent: 200031491 (2000-01-01), None
patent: 2001217430 (2001-08-01), None
patent: WO9930370 (1999-06-01), None
patent: WO 99/53539 (1999-10-01), None
patent: WO9953539 (1999-10-01), None
XP-002111024, “Epitaxial Si-Ge Etch Stop Layers With Ethylene Diamine Pyrocatechol For Bonded And Etchback Silicon-On-Insulator”, D. Feijoo et al., AT&T Bell Laboratories, Murray Hill, NJ 07974. revised Feb. 2, 1994.
T. Mizuno, “High Performance Strained-Si p-MOSFET's on SiGe-On-Insulator Substrates fabricated by SIMOX Technology”, IEDM Tech. Digest 99-934, 1999.
Wolf, et al. Silicon Processing for the VLSI Era, vol. 1-Process Technology, 2nd ed., Lattice Press: Sunset Baech CA, 2000, pp. 386-391.
Chu Jack Oon
DiMilia David R.
Huang Lijuan
International Business Machines - Corporation
Pham Thanhha
Scully , Scott, Murphy & Presser, P.C.
Trepp, Esq. Robert M.
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