Layer arrangement, memory cell, memory cell arrangement and...

Details Layer arrangement, memory cell, memory cell arrangement and... Layer arrangement, memory cell, memory cell arrangement and...

2005-05-31

2005-05-31

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S303000, C438S206000

Reexamination Certificate

active

06900495

ABSTRACT:
The invention relates to a layer arrangement, a memory cell, a memory cell arrangement and a method for producing a layer arrangement. The layer arrangement has a monocrystalline substrate, a highly doped region in the substrate and a metallically conductive structure in the highly doped region, a partial region of the highly doped region that is arranged in a surface region of the substrate being monocrystalline.

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Schuppen, A., Vescan, L., Jebasinski, R., v.d. Hart, A., Luth, H. Effect of doping profiles on Si/CoSi2permeable base transistors. Microeletronic Engineering 18, pp. 259-266 (1992).
Risch, L. Rosner, W., Schulz, T., Transistor Verkehrt. In Spektrum der Wissenschaft, Edition Jun. 1999, p. 941.

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