Semiconductor device manufacturing: process – Making device array and selectively interconnecting
Reexamination Certificate
2000-04-12
2002-10-22
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
C438S615000
Reexamination Certificate
active
06468836
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to interconnecting semiconductor chips and supporting substrates, and more particularly relates to a structure for compliantly interconnecting semiconductor chips and supporting substrates while substantially obviating the problems encountered due to their differences in the thermal coefficients of expansion.
BACKGROUND OF THE INVENTION
Semiconductor chips typically are connected to external circuitry through contacts on a surface of the chip. To save area on a supporting substrate, such as a printed circuit board, these chips are typically directly connected/soldered to the substrates and from there connected to external circuitry on other parts of the substrate. The contacts on the chip are generally either disposed in regular grid-like patterns, substantially covering the front surface of the chip (commonly referred to as an “area array”) or in elongated rows extending parallel to and adjacent each edge of the chip front surface.
The body of the chip package may be comprised of a molded plastic or ceramic material. Many of the techniques for solder attachment run into problems because of the thermal expansion mismatch between the material the package is composed of and the material the supporting substrate is made of, such as a printed wiring board (“PWB”). In other words, when heat is applied to the chip/substrate combination, they both expand; and when the heat is removed, the device and the substrate both contract. The problem that arises is that the device and the substrate expand and contract at different rates and at different times, thereby stressing the interconnections between them.
In attempting to use the area on printed circuit boards more efficiently, IC manufacturers have recently been switching from larger, more cumbersome interconnection conventions, such as pin grid arrays (“PGAs”) and the perimeter leaded quad flat packs (“QFPs”), to smaller conventions, such as ball grid arrays (“BGAs”). Using BGA technology, semiconductor chips are typically interconnected with their supporting substrates using solder connections. However, when solder alone is used to interconnect the package's contacts to the substrate, the columns or balls of solder are generally designed to be short to maintain the solder's structural integrity. This results in minimal elastic solder connection properties which further results in increased susceptibility to solder cracking due to fatigue brought on by the thermal cycling (heating and cooling cycles of the device/substrate).
An interconnection solution put forth in U.S. Pat. No. 4,642,889, entitled “Compliant Interconnection and Method Therefor” issued Apr. 29, 1985 to Grabbe seeks to alleviate the aforementioned solder cracking problem by embedding wires within each solder column to reinforce the solder thereby allowing higher solder pedestals and more elasticity. Another solution includes spirally wrapping wire around the outside of the solder. A further solution put forth includes providing a combination of solder and high lead solder, as found in U.S. Pat. No. 5,316,788, entitled “Applying Solder to High Density Substrates” issued to Dibble et al. All of these prior art solutions are aimed at increasing the compliancy of the interconnections in order to reduce the shear stress endured by the interconnections because of the thermal cycling. However, as packages are reduced in size, the number of devices packed into a given area will be greater. The heat dissipated by the each of these devices will have a greater effect on the surrounding devices and will thus increase the need for a highly compliant interconnection scheme for each device. Further, as the number of device interconnections increases, as is the case when chips are integrated into multichip modules, the overall rigidity of the total interconnection also increases thereby again increasing the need for a highly compliant interconnection scheme. None of the aforementioned prior solutions provides an interconnection scheme which is compliant enough to effectively deal with these problems.
Certain designs have reduced solder connection fatigue by redistributing the thermal cycling stress into a portion of the chip package itself. An example of such a design is shown in commonly assigned U.S. Pat. Nos. 5,148,265 and 5,148,266, the both disclosures of which are incorporated herein by reference. One disclosed embodiment of these patents shows the use of a chip carrier in combination with a compliant layer to reduce the coefficient of thermal expansion (“CTE”) mismatch problems. Typically, the compliant layer includes an elastomeric layer which, in the finished package, is disposed between the chip carrier and the face surface of the chip. The compliant layer provides resiliency to the individual terminals, allowing each terminal to move in relation to its electrically connected chip contact to accommodate CTE mismatch as necessary during testing, final assembly and thermal cycling of the device.
Despite the positive results of the aforementioned commonly owned inventions, still further improvements would be desirable.
SUMMARY OF THE INVENTION
The present invention provides a semiconductor chip package having a means to help compensate for the CTE mismatch between the chip and the PWB.
In one embodiment, the package includes a sheet-like substrate having at least one gap extending from a first surface to a second surface of the substrate. The substrate has conductive terminals which may be contacted from the second surface side of the substrate. The substrate further has conductive leads electrically connected to and extending from each terminal and across the gap or gaps. Each lead is connected to a bond pad on the opposite side of the gap, wherein each lead has an expansion section within the gap which is laterally curved with respect to the plane of the substrate. Typically, the expansion sections laterally curve at least twice in opposite directions and in one embodiment create substantially “s” shaped lead portions. A semiconductor chip having a back surface and a face surface is connected to the substrate. The chip further has a plurality of chip contacts located on a periphery of the face surface. The chip contacts are electrically and mechanically connected to respective bond pads on the substrate. This structure allows the package to compensate for CTE mismatch problems by the flexing and bending of the expansion sections of the leads within the gap(s). The substrate may also be adhered to a chip surface, either rigidly or compliantly adhered as through the use of a compliant layer between the chip and the substrate. Such a compliant layer would aid in compensating for the CTE mismatch problems. Further, the expansion sections of the leads are typically encapsulated with a compliant encapsulant to provide added support for their bending and flexing motion during thermocycling.
In a “face-down” embodiment, the first surface of the substrate overlies the face surface of the chip. If it desired that the package dimensions be kept as small as possible, the terminals will lie in a central region of the substrate bounded by the chip contacts, in a so called “fan-in” structure. Each bond pad is thus aligned with and bonded to a respective chip contact. Typically, the gap in the substrate then extends between the bond pads and the terminals such that the gap encircles the central region of the substrate creating a first substrate bearing the terminals and a second substrate bearing the bond pads. However, more than one gap may be used if it is not desired to have the bond pad portion of the substrate be discrete from the terminals portion of the substrate.
In this “face-down” structure, it may also be desired for the terminals to outside of the periphery of the chip, in a so called “fan-out” structure. In this arrangement, the substrate may be continuous beneath the chip or may have an aperture so that the face surface of the chip may be accessed after the bond pads are connected to respective chip contac
Distefano Thomas H.
Fjelstad Joseph
Smith John W.
Lerner David Littenberg Krumholz & Mentlik LLP
Tessera Inc.
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