Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-10-09
2004-08-31
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S666000, C438S640000, C438S584000
Reexamination Certificate
active
06784102
ABSTRACT:
FIELD
This invention relates to the field of integrated circuit processing. More particularly, this invention relates to structure designs that reduce inter structure separations.
BACKGROUND
Integrated circuits are typically formed of layers of different materials that are built up, one on top of the other. The different layers are all design to provide different functions within the finished integrated circuits. However, because any given layer tends to be formed of a different material than the layers to which it is immediately adjacent, either vertically or laterally, it is possible that when sufficient forces are applied to the layers, they may pull apart from each other to some degree. This, of course, tends to disrupt the proper operation of the integrated circuit.
For example, electrically conductive structures are often formed of metallic materials and alloys, among other materials. The electrically conductive structures are electrically isolated one from another by dielectrics, or electrically insulating layers, such as those formed of oxides, like silicon oxide. Electrically conductive structures called vias are used to conduct electrical signals from an overlying electrically conductive layer, through an intervening dielectric layer, to an underlying electrically conductive layer. However, if sufficient forces are imparted on the overlying electrically conductive layer, such as if upward forces are applied to it, the via may tear loose from the underlying electrically conductive layer.
As a further and more specific example, electrically conductive bonding disposed near the top surface of an integrated circuit are typically formed of a metal or a metal alloy. When an electrical connection is formed on the bonding pad, such as when a wire bond is made, there is typically a relatively strong vertical lifting force applied to the bonding pad when the bonding tool, such as a bonding tip or capillary, is pulled away from the bonding pad. This upward force can tear the bonding pad away from the adjacent layers, can rip the vias connected to the bonding pad out of the underlying layers, and cause a general disruption to many of the layers underlying and in near proximity to the bonding pad.
What is needed, therefore, is a system by which different layers within an integrated circuit are more resistant to forces that might otherwise pull them apart, one from another.
SUMMARY
The above and other needs are met by a method of increasing mechanical interlocking between a first structure and a second adjacent structure in an integrated circuit. The first structure is formed with a first surface having a first horizontal component, and the second structure is formed with a second surface having a second horizontal component. The first surface laterally engages the second surface and the first horizontal component is complementary to the second horizontal component, such that the first structure prohibits vertical movement of the second structure.
In this manner, the laterally interlocking horizontal components of the first and second structures provide a mechanical mechanism by which vertical forces that are applied to one of the structures are opposed with the other structure. Thus, the degree to which such vertical forces are able to separate the first and second structures is reduced.
In various preferred embodiments of the method, the first structure is an electrically conductive via and the second structure is an electrically nonconductive layer through which the via passes. Alternately, the second structure is an electrically conductive via and the first structure is an electrically nonconductive layer through which the via passes. In another embodiment, the first structure is an electrically conductive layer and the second structure is an electrically nonconductive layer, or the second structure is an electrically conductive layer and the first structure is an electrically nonconductive layer. The first structure may substantially overlie the second structure, or the first structure may substantially underlie the second structure. Alternately, the first structure is substantially coplanar with the second structure.
According to another aspect of the invention there is provided a method of increasing mechanical interlocking between a plurality of layers in an integrated circuit. The plurality of layers is formed with at least a bottom layer and an overlying top layer. An uninterrupted void extending through the top layer and through the bottom layer is formed. The void has a first surface having a first horizontal component within the top layer and a second surface having a second horizontal component within the bottom layer. A first structure is formed within the void, where the first structure has a first mating surface having a first complementary horizontal component and a second mating surface having a second complementary horizontal component.
The first mating surface laterally engages the first surface of the top layer and the first complementary horizontal component is complementary to the first horizontal component of the first surface of the top layer. Similarly, the second mating surface laterally engages the second surface of the bottom layer and the second complementary horizontal component is complementary to the second horizontal component of the second surface of the bottom layer. In this manner the first structure prohibits vertical separation of the plurality of layers.
In various preferred embodiments of this aspect of the invention, the plurality of layers include at least one intervening layer disposed between the bottom layer and the top layer. The plurality of layers may be electrically nonconductive layers where the first structure is an electrically conductive via. Alternately, the top layer and the bottom layer are electrically conductive layers, with at least one electrically nonconductive layer disposed between the top layer and the bottom layer, and the first structure is an electrically conductive via. In yet another embodiment, the top layer and the bottom layer comprise electrically conductive layers, with at least one electrically nonconductive layer disposed between the top layer and the bottom layer, and the first structure is electrically nonconductive. Preferably, a plurality of voids are formed and a plurality of first structures are formed within the voids.
In yet another aspect of the invention, a method is described of increasing mechanical interlocking between a first underlying layer and a second overlying layer in an integrated circuit. The first layer is formed with an upper surface having a series of first surfaces, where each of the first surfaces have an associated first horizontal component. The second layer is formed on top of the first layer, with a lower surface having a series of second mating surfaces, each of the second mating surfaces having an associated second complementary horizontal component. The second mating surfaces of the second layer laterally engage the first surfaces of the first layer, and the second complementary horizontal components of the second surfaces are complementary to the first horizontal components of the first surfaces. In this manner, the engagement between the first surfaces of the first layer and the second mating surfaces of the second layer prohibit vertical separation of the first layer and the second layer.
Preferably, the first surfaces are formed by etching the first layer. Alternately, the first surfaces are formed by forming additional material on the first layer. In one embodiment, the first layer is an electrically conductive layer and the second layer is an electrically nonconductive layer. Alternately, the first layer is an electrically nonconductive layer and the second layer is an electrically conductive layer. Preferably, the first surfaces of the first layer are formed in elongate parallel rows, but may be formed in smaller, discrete portions.
REFERENCES:
patent: 6204554 (2001-03-01), Ewer et al.
patent: 6255586 (2001-07-01), Kim et al.
patent: 6367152 (2002-04-01), Katao
Ali Anwar
Lau Tauman T.
Yeung Max M.
Everhart Caridad
LSI Logic Corporation
Luedeka Neely & Graham
LandOfFree
Laterally interconnecting structures does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Laterally interconnecting structures, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Laterally interconnecting structures will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3293246