Lateral super-junction semiconductor device

Details Lateral super-junction semiconductor device Lateral super-junction semiconductor device

2001-04-27

2004-06-29

Jackson, Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S401000, C257S341000, C257S343000

Reexamination Certificate

active

06756636

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor structure applicable to semiconductor devices such as MOSFET's (insulated gate field effect transistors), IGBT's (insulated gate bipolar transistors), bipolar transistors and diodes. More specifically, the present invention relates to a semiconductor device, which includes an alternating conductivity type layer that provides a current path in the ON-state of the semiconductor device and is depleted in the OFF-state of the semiconductor device.
BACKGROUND
Semiconductor devices may be roughly classified into lateral devices, in which the main electrodes thereof are arranged on one major surface, and vertical devices that distribute the main electrodes thereof on two major surfaces facing opposite to each other. In a vertical semiconductor device, a drift current flows vertically between the main electrodes in the ON-state of the device. To provide the vertical semiconductor device with a high breakdown voltage, it is necessary to thicken the highly resistive layer between the main electrodes. However, a thick, highly resistive layer inevitably causes high on-resistance that further increases loss. In other words, there exists a tradeoff relationship between the on-resistance (current capacity) and the breakdown voltage. The tradeoff relationship between the on-resistance and the breakdown voltage exists in semiconductor devices such as MOSFET's, IGBT's, bipolar transistors and diodes.
European Patent 0 053 854, U.S. Pat. Nos. 5,216,275, 5,438,215, and Japanese Unexamined Laid Open Patent Application H09-266311 disclose semiconductor devices, which include an alternating conductivity type layer formed of heavily doped n-type regions and heavily doped p-type regions alternately arranged to reduce the tradeoff relationship between the on-resistance and the breakdown voltage. The alternating conductivity type layer is depleted in the OFF-state of the semiconductor device to sustain the breakdown voltage. Hereinafter, the semiconductor device including an alternating conductivity type layer, that provides a current path in the ON-state of the device and is depleted in the OFF-state of the device, will be referred to as the “super-junction semiconductor device”.
The tradeoff relationship between the on-resistance and the breakdown voltage also exists in lateral semiconductor devices, in which current flows laterally between the main electrodes arranged on one of the major surfaces in the ON-state thereof. Forming the drift layer thereof of an alternating conductivity type layer including n-type regions and p-type regions arranged alternately reduces the tradeoff relation in the lateral semiconductor devices.
FIG. 12
is a perspective view of a fundamental lateral super-junction MOSFET. FIG.
13
(
a
) is a cross sectional view along A—A of FIG.
12
. In these figures, oxide films and metal films, excluding a polycrystalline silicon gate electrode
9
, are not illustrated for the sake of easy understanding. Referring to
FIG. 12
, the lateral super-junction MOSFET has a lateral double-diffused MODFET structure formed in the surface portion of a n-type layer
4
on a p-type substrate
5
. A drain section
11
includes a n
+
-type drain region
8
with low electrical resistance and a not shown drain electrode on n
+
-type drain region
8
. A source section
13
includes a p-type well region
6
, a n
+
-type source region
7
in the surface portion of p-type well region
6
, and a not shown source electrode in contact with n
+
-type source region
7
and p-type well region
6
. An alternating conductivity type layer
12
is between drain section
11
and source section
13
. A drift section, that is alternating conductivity type layer
12
, includes a comb-shaped n-type drift region
1
and p-type partition regions
2
between the teeth of comb-shaped n-type drift region
1
. Hereinafter, the teeth of comb-shaped n-type drift region
1
will be referred to simply as the “n-type drift regions
1
”. A drift current flows through n-type drift regions
1
of alternating conductivity type layer
12
. Each region of alternating conductivity type layer
12
is from 1 to 10 &mgr;m in width and, preferably, from 1 to 4 &mgr;m in width. Alternating conductivity type layer
12
is from 1 to 10 &mgr;m in depth and, preferably, from 1 to 4 &mgr;m in depth. Alternating conductivity type layer
12
is around 50 &mgr;m in width for the MOSFET of the 600 V class and around 100 &mgr;m in width for the MOSFET of the 1000 V class.
In the lateral super-junction MOSFET configured as described above, a channel inversion layer
3
is formed below a gate electrode
9
when a voltage is applied between the drain electrode and the source electrode, and an appropriate voltage to gate electrode
9
. Electrons flow into n-type drift regions
1
from n
+
-type source region
7
via channel inversion layer
3
. As a result, a drift current flows due to the electric field between the drain electrode and the source electrode (the ON-state of the device). When the voltage is removed from gate electrode
9
, channel inversion layer
3
vanishes. Depletion layers expand from the pn-junctions between n-type drift regions
1
and p-type well region
6
and from the pn-junctions between n-type drift regions
1
and p-type partition regions
2
into n-type drift regions
1
and n-type layer
4
due to the voltage between the drain electrode and the source electrode. As a result, n-type drift regions
1
and n-type layer
4
are depleted (the OFF-state of the device).
The depletion layers from the pn-junctions between n-type drift regions
1
and p-type partition regions
2
expand in the width direction of n-type drift regions
1
. Since n-type drift regions
1
are narrow, n-type drift regions
1
are depleted very fast. Since p-type partition regions are also depleted, alternating conductivity type layer
12
facilitates providing the lateral super-junction MOSFET with a high breakdown voltage. Since n-type drift regions
1
may be doped heavily, alternating conductivity type layer
12
facilitates lowering the on-resistance of the lateral super-junction MOSFET.
An ideal relation between the on-resistance and the breakdown voltage per a unit area is expressed by the following equation:
R=BV
2
/(2
N&bgr;
3
E
C
3
&egr;
0
&egr;
Si
&mgr;)  (1)
where, R is the on-resistance per the unit area, BV the breakdown voltage, N the number of n-type drift regions
1
in alternating conductivity type layer
12
, &bgr; the unknown coefficient, E
C
the critical electric field at the impurity concentration of the n-type drift region, &egr;
0
the dielectric permeability of the vacuum, &egr;
Si
the relative dielectric permeability of silicon, and the electron mobility.
As equation (1) indicates, the on-resistance is reduced dramatically by increasing the number N of n-type drift regions
1
in the alternating conductivity type layer. This principle is described in detail in Japanese Unexamined Laid Open Patent Application H09-266311.
FIG.
13
(
b
) is a cross sectional view of a conventional lateral super-junction MOSFET, that employs a double reduced surface electric field structure (a double RESURF structure). Referring to FIG.
13
(
b
), a lightly doped p-type layer
15
is interposed between n-type layer
4
and alternating conductivity type layer
12
. This structure facilitates providing the device with a high breakdown voltage, since depletion layers expand into n-type layer
4
from the pn-junction between n-type layer
4
and p-type layer
15
and from the pn-junction between n-type layer
4
and p-type substrate
5
.
Japanese Unexamined Laid Open Patent Application H10-321567 describes that it is effective to equalize the impurity concentrations and the widths of n-type drift regions
1
and p-type partition regions
2
for reducing the tradeoff relation between the on-resistance and the breakdown voltage and for realizing a high breakdown voltage. The means and the techniques disclosed in the foregoin

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