Lateral semiconductor device

Details Lateral semiconductor device Lateral semiconductor device

2001-07-03

2004-03-30

Pham, Long (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

Reexamination Certificate

active

06713794

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-202341, filed Jul. 4, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to an increase in the ruggedness of a lateral semiconductor device such as a lateral IGBT.
FIG. 1
is a sectional view showing a conventional lateral IGBT.
As shown in
FIG. 1
, an isolated N
−
-type island region
102
is formed on a dielectric isolation substrate, e.g., SOI substrate
101
. A P-type base layer
103
and N-type buffer layer
104
are formed apart from each other in the N
−
-type island region
102
. An N
+
-type source layer
105
is formed in the P-type base layer
103
, and a P
+
-type base contact layer
106
is formed in the N
+
-type source layer
105
so as to reach the P-type base layer
103
. A source electrode (source wiring layer; which may also be called an emitter electrode or emitter wiring layer)
107
is electrically connected to the P-type base layer
103
via the P
+
-type base contact layer
106
, and to the N
+
-type source layer
105
. A P
+
-type drain layer
108
is formed in the N-type buffer layer
104
. A drain electrode (drain wiring layer; which may also be called a collector electrode or collector wiring layer)
109
is electrically connected to the P
+
-type drain layer
108
. A portion of the P-type base layer
103
that is sandwiched between the N
−
-type island region
102
and the N
+
-type source layer
105
functions as the channel of a MOS transistor. A gate electrode
110
is formed from the channel to the N
−
-type island region
102
via a gate oxide film
111
.
A summary of the operation of the lateral IGBT is as follows.
For example, the drain electrode
109
is set to a high potential, whereas the source electrode
107
is set to a low potential. If the gate electrode
110
changes to “HIGH” level in this state, the conductivity type of the channel is reversed, and electrons are injected from the N
+
-type source layer
105
to the N
−
-type island region
102
via the channel, as indicated by an arrow
112
. As a result, a PNP bipolar transistor having the N-type buffer layer
104
and N
−
-type island region
102
as a base, the P
+
-type drain layer
108
as a collector, and the P-type base layer
103
as an emitter is turned on. Then, the lateral IGBT is turned “on”.
If the gate electrode
110
changes to a “LOW” level, the conductivity type of the channel returns to the original one, injection of electrons into the N
−
-type island region
102
stops, and the PNP bipolar transistor is turned off. Thus, the lateral IGBT is turned “off”.
The gate electrode
110
is formed above the surface (major surface) of the N
−
-type island region
102
via the gate oxide film
111
. A strong electric field is generated in an end region
113
of the gate electrode
110
.
In the lateral IGBT, electrons concentratedly flow through the surface (major surface) of the N
−
-type island region
102
, as indicated by the arrow
112
. In other words, electrons concentratedly flow immediately below the gate electrode
110
. Consequently, a current concentrates immediately below the end region
113
, readily causing a breakdown around the end region
113
. This inhibits an increase in ruggedness.
BRIEF SUMMARY OF THE INVENTION
A semiconductor device according to an aspect of the invention comprises: a semiconductor base of a first conductivity type having a major surface; a first semiconductor region of a second conductivity type formed in the semiconductor base; a second semiconductor region formed in the semiconductor base, the second semiconductor region separate from the first semiconductor region; a third semiconductor region of the first conductivity type formed in the first semiconductor region; a first main electrode which is formed on the major surface of the semiconductor base and electrically connected to the first and third semiconductor regions; a second main electrode which is formed on the major surface of the semiconductor base and electrically connected to the second semiconductor region; an insulating film formed on the major surface of the semiconductor base; a gate electrode formed on the insulating film at least on the major surface of the semiconductor base and the first semiconductor region between the semiconductor base and the third semiconductor region; and a fourth semiconductor region of the second conductivity type formed in the semiconductor base between the first and second semiconductor regions below an end region of the gate electrode.


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patent: 6265752 (2001-07-01), Liu et al.
patent: 6392275 (2002-05-01), Jang
patent: 406151728 (1994-05-01), None
patent: 406232351 (1994-08-01), None
patent: 1020000033197 (2000-06-01), None

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