Lateral semiconductor device

Details Lateral semiconductor device Lateral semiconductor device

2001-05-30

2004-02-17

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

With means to increase breakdown voltage threshold

With electric field controlling semiconductor layer having a...

C257S492000, C257S496000, C257S409000, C257S339000, C257S629000

Reexamination Certificate

active

06693340

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims benefit of priority to British application Serial No. GB0111556.7, filed May 11, 2001.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a lateral semiconductor device.
The present invention relates generally to the field of high voltage semiconductor devices and more particularly to high voltage lateral devices manufactured by the use of SOI (Silicon-on-Insulator) technology.
BACKGROUND OF THE INVENTION
As shown schematically in
FIG. 1
, a typical lateral high-voltage device
1
fabricated using SOI technology has a basic configuration of a p+ region
2
and an n+ region
3
at opposing ends separated by a central n drift region
4
of lower conductivity, all of which are formed in an SOI layer
5
which is formed on an oxide layer
6
which itself is formed on a silicon substrate
7
. The p+ region
2
is shorted to the substrate
7
below the BOX (buried oxide layer)
6
. In the blocking/off-state mode, a terminal (not shown) connecting the p+ region
2
and the substrate
7
is grounded and a high voltage reverse bias is applied to a terminal (not shown) connected to the n+ region
3
. As the reverse bias is increased, a depletion layer develops across the p+
junction
2
/
4
. The bulk of the depletion layer forms within the central n region
4
so that a significant portion of the applied reverse bias is sustained inside the central n region
4
. Simultaneously, due to a field effect action across the buried oxide
6
, an inversion/accumulation layer forms directly beneath the buried oxide layer
6
in the p or n type substrate
7
. This layer of highly mobile charge maintains an equipotential surface at ground potential beneath the buried oxide layer
6
and screens nearly all of the electric field from the bulk of the substrate
7
and behaves in effect as a field plate. The field plate effect causes a crowding of the potential lines in the area surrounding the n+ region
3
which, during the blocking state, is connected to the reverse bias. The electric field inside the depleted region of the central n region
4
is thus distorted and results in the formation of a second electric field peak near the n+ region
3
in addition to the original electric field peak occurring at the p+
junction
2
/
4
. This is the so-called “RESURF” phenomenon observed in high voltage SOI devices. Unlike the RESURF effect in Junction Isolation (JI) technology, the RESURF effect in SOI is weak and this is mainly because the buried oxide layer
6
prevents a direct coupling of fixed ion charge between the substrate
7
and the upper SOI layer
5
. The absence of this coupling excludes the formation of a depletion layer within the substrate
7
. Thus, in such devices, the high voltage sustaining capability must come from either the SOI
5
or the buried oxide layer
6
.
In the past, methods for achieving high blocking voltages have relied on a relatively thick SOI layer
5
to support the reverse bias. For instance, to reach 500 Volts, the SOI layer
5
should typically have a depth of 10 to 20 &mgr;m. However, if for example a SOI layer
5
in excess of 5 &mgr;m thickness is ruled out because of isolation problems, then the reverse bias must be supported almost entirely by the buried oxide layer
6
.
Consider now the electric field at the SOI/BOX interface
5
/
6
for the device
1
in FIG.
1
. In the ideal case, the horizontal component of the electric field at this interface will be constant, and the voltage along the line AB in
FIG. 1
will increase linearly towards B. Since the reverse bias is mainly supported by the oxide layer
6
, it follows that the vertical component of the electric field at the interface and within the oxide layer
6
must also increase linearly along AB. Thus, the main criterion for a perfect electric field distribution in SOI layers
5
of thin to medium thickness translates to the requirement of a vertical electric field &xgr;y at the SOI/BOX interface which is proportional to distance from the grounded end A.
One way of achieving this is by use of a thin linearly graded profile in the n drift region
4
. Furthermore, if the horizontal electric field distribution is constant, then any electric field due to the charge in the SOI layer
5
along a vertical line must terminate at the layer of mobile charges formed at the substrate/BOX interface
7
/
6
. This allows the vertical electric field distribution along any vertical line in the SOI layer
5
to be approximated as a triangular distribution. Another way of obtaining a linear distribution of the vertical electric field along the SOI/BOX interface
5
/
6
is via the use of a tapered or stepped buried oxide layer
6
.
Referring again to
FIG. 1
, applying Gauss's law along the line BC at the high voltage end, the required distribution of the vertical electric field in the SOI layer
5
along the SOI/BOX interface
5
/
6
can be deduced as:
ξ
y
⁡
(
x
)
=
ϵ
ox
⁢
V
br
ϵ
si
⁢
t
ox
⁢
(
x
L
drift
)
(
1
)
and the corresponding doping profile is given by,
N
SOI
⁡
(
x
)
=
ϵ
ox
⁢
V
br
q
⁢
 
⁢
t
soi
⁢
t
ox
⁢
(
x
L
drift
)
.
(
2
)
Because the electric field at the SOI/BOX interface
5
/
6
can be high, especially in high voltage devices, a thin SOI layer
5
must in practice be used as it allows a higher critical electric field to be sustained across it.
FIG. 2
shows, for several doping concentrations, how the critical electric field in silicon increases as the thickness of the silicon is reduced.
S. Merchant, E. Arnold, S. Mukherjee, H. Pein and R. Pinker, “Realisation of High Breakdown Voltage (≦700 volts) in Thin SOI Devices”, ISPSD 91, p. 31 describe a previous attempt to achieve a uniform surface electric field distribution and exploit the voltage-supporting capability of the buried oxide by the use of a linearly graded doping profile in an ultra-thin (<1 &mgr;m) SOI layer. In accordance with equation (1) above, the doping profile increases from the grounded p+ region towards the n+ region connected to the reverse bias. In another attempt to achieve greater uniformity of the electric field distribution, F. Udrea et al in “3D RESURF Double-Gate MOSFET: A revolutionary power device concept”, Electronic Letters, vol.34, no.8, April 1998, propose the use of parallel, alternating n and p stripes in the SOI region, in which the charge in the n stripe balances exactly the charge in the p stripe. However, use of charge-balanced, parallel n and p stripes results in large electric field peaks at the n+ and p+ ends.
In practice, it is difficult to fabricate a device in which the doping profile of any region varies uniformly linearly as required by these prior art proposals.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, there is provided a lateral semiconductor device, the device comprising a semiconductor layer on an insulating layer on a semiconductor substrate, the semiconductor layer having a region of a first conduction type and a region of a second conduction type with a drift region therebetween, the drift region being provided by a region of the first conduction type and a region of the second conduction type, the first and second conduction type drift regions being so arranged that when a reverse voltage bias is applied across the first and second conduction type regions of the semiconductor layer, the second conduction type drift region has an excess of charge relative to the first conduction type drift region which varies substantially linearly from the end of the drift region towards the first conduction type region of the semiconductor layer to the end of the drift region towards the second conduction type region of the semiconductor layer.
According to a second aspect of the present invention, there is provided a lateral semiconductor device, the device comprising a semico

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