Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-10-04
2001-08-07
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S408000, C257S491000
Reexamination Certificate
active
06271552
ABSTRACT:
FIELD OF THE INVENTION
The current invention is in the field of lateral RF MOS devices.
DESCRIPTION OF THE BACKGROUND ART
Power high frequency devices have been built using a variety of semiconductor technologies. For a long time the preferred vehicle for their realization has been the NPN bipolar junction transistor (BJT). Its primary advantage was the achievable high intrinsic transconductance (g
m
) that permitted the fabrication of high power devices utilizing small silicon areas.
As processing technology improved, in the early 1970's a number of MOSFET vertical structures begun to challenge the dominance of the BJT at the lower RF frequencies, trading the cost of the large silicon area, necessary to provide the current capability in MOSFETs, for the cost of simple processing. The advantages that the MOSFET structure provided to the user were: higher power gain, ruggedness (defined as the capacity to withstand transients) and ease of biasing.
In the continuous quest for high frequency operation at high power the MOSFET structure has displaced the BJT since the early 1970's in applications where its performance has been competitive.
Recently, new prior art RF MOS devices have been placed on the market by several vendors. The new prior art RF MOS devices utilize the standard lateral MOS device with a diffused via that connects the source to the backside of the chip such that the back side becomes both electrical and thermal ground. The prior art structure also uses a polysilicide gate process as a compromise between the fabrication benefits of the self aligned polysilicon gate and the high frequency performance of the metal gate structure. The prior art structure has extended the frequency of operation of MOS devices into the 2 GHz region thus covering two frequency bands of great commercial importance: the cellular and PCS/PCN mobile telephone bands.
The via backside contact design and the polysilicide gate processing technology have allowed the prior art device to attain its performance. Firstly, by transferring the source connection to the backside of the chip through a diffused via, the packaging of the device has been simplified reducing parasitic inductance and resistance to ground. The thermal dissipation has been also improved because an electrical isolation layer in the package has been removed. Secondly, the output capacitance of RF MOS device for the common-source mode of amplification operation has been made comparable to the output capacitance obtained with BJT structures. This results in improved collector efficiency and in wider usable bandwidth (BW) of the RF MOS device operating as an amplifier. This improvement comes about as the lateral RF MOS device at high drain-source applied bias has a lower drain-source capacitance (C
ds
) than the drain-source capacitance of the prior art RF MOS devices. Finally, the use of polysilicide allows the efficient feeding of long gate fingers.
The design of the existing lateral RF MOS devices was further improved in the lateral RF MOS device disclosed in the U. S. Pat. No. 5,949,104, issued on Sep. 7, 1999 and incorporated by reference herein in its entirety. In the '104 patent the connection from the source to the backside of the silicon substrate was improved by using a metal plug. The usage of the metal plug to connect the source to the backside of the silicon substrate further reduced the space needed for that connection, and eliminated the lateral as well as the downward movement of the source to backside via diffusion. The metal plug design allowed the inclusion of more usable device active area per unit chip area, lead to an increase of available device output power per unity chip area, resulted in a further decrement of the minimal value of the drain-source capacitance (C
ds
), and in a wider usable BW of the device operating as an amplifier.
However, all prior art lateral RF MOS devices had an inadequate maximum drain-source voltage breakdown due to a high electric field concentration near the drain junction. The increased breakdown voltage would allow higher current density to flow in the source-drain channel thus increasing the power output that could be available at the lateral RF MOS device of the same size.
Thus, what is needed is to improve the design of a lateral RF MOS device which would lead to a lateral RF MOS device having the prior art size but a larger power output.
SUMMARY OF THE INVENTION
To address the shortcomings of the available art, the present invention provides for a large power output lateral RF MOS device with the prior art size.
One aspect of the present invention is directed to a lateral MOS structure having two enhanced drain drift regions.
In the first preferred embodiment, the lateral MOS structure comprises a semiconductor material of a P-type having a first dopant concentration P
−
and a top surface. A conductive gate overlies the top surface of the semiconductor material and is insulated from it. A first region of a second conductivity type and having a second dopant concentration is formed completely within the semiconductor material of the first conductivity type. The first region forms a first enhanced drain drift region of the RF MOS transistor structure. The lateral MOS structure further comprises a second region of the second conductivity type and having a third dopant concentration being less than the second dopant concentration formed in the semiconductor material. The second region forms a second enhanced drain drift region of the RF MOS transistor. The second enhanced drain drift region contacts the first enhanced drain drift region.
The lateral MOS structure further comprises a drain region contacting the second enhanced drain drift region, a body region having a first end underlying the conductive gate, a source region located within the body region, a contact enhancement region located within the body region, and a conductive plug region formed in the source region and the body region of the semiconductor material.
In one embodiment, the conductive plug region connects the source region and the body region of the semiconductor material to the backside of the MOS structure.
In another embodiment, the conductive plug region connects a surface of the source region and a lateral surface of the body region of the semiconductor material to a highly conductive substrate of the lateral MOS structure.
In the second preferred embodiment of the present invention, the lateral MOS structure comprises a semiconductor material of a P-type having a first dopant concentration P
−
and a top surface. A conductive gate overlies the top surface of the semiconductor material and is insulated from it. A first region of a second conductivity type and having a second dopant concentration is formed completely within the semiconductor material of the first conductivity type. The first region forms a first enhanced drain drift region of the RF MOS transistor structure. The lateral MOS structure further comprises a second region of the second conductivity type and having a third dopant concentration being higher than the second dopant concentration formed in the semiconductor material. The second region forms a second enhanced drain drift region of the RF MOS transistor. The second enhanced drain drift region contacts the first enhanced drain drift region.
The lateral MOS structure further comprises a drain region contacting the second enhanced drain drift region, a body region having a first end underlying the conductive gate, a source region located within the body region, a contact enhancement region located within the body region, a contact region contacting the body region, and a conductive plug region connecting the contact region and a backside of the semiconductor material.
In one embodiment, the contact region further connects the top surface of the semiconductor material to the highly conductive substrate.
In another embodiment, the contact region is located within the semiconductor material.
In the preferred embodiment, the first conductivity type is of P typ
Dickey Thomas
Tankhilevich Boris G.
Tran Minh Loan
Xemod, INC
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