Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-06-17
2001-06-12
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S339000, C257S345000
Reexamination Certificate
active
06246091
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to semiconductor devices and processes and more specifically to a lateral MOSFET structures having raised source/drain regions.
BACKGROUND OF THE INVENTION
As semiconductor devices are scaled to smaller dimensions, generally in the sub-0.1 &mgr;m region, it is highly desirable and generally necessary to fabricate such devices with smaller junction depths and a controllable pocket implant adjacent to the shallow junctions to reduce short-channel effects (i.e., reduced threshold voltage rolloff) and reduced in gate length. The pocket implant is a doped implanted region which is oppositely doped to the junction regions. A problem that arises with such small geometries is that, with very short channel lengths, the implant profile cannot be adequately controlled and shallow junctions and/or well controlled thicknesses of doped layers generally cannot be formed by simple implantation.
An example of such a prior art device is shown in
FIGS. 1
a
and
1
b
wherein there is shown a semiconductor substrate
1
, for example doped p-type, having a gate electrode
3
spaced from the substrate by a dielectric layer
5
. Shallow doped extension regions
7
(denoted herein as drain extension regions and, for example, doped n-type) may be formed on each side of the gate electrode
3
with or without sidewall dielectric spacers
2
provided adjacent to the gate electrode
3
prior to formation of the doped extension regions
7
. Pocket regions
9
of doping type opposite (e.g., p-type) to that of the drain extension regions
7
may be formed by means of implantation prior to or after formation of the drain extension regions
7
. Typically, the pocket region
9
extends beyond the drain extension regions
7
in both the lateral and vertical directions, whereby a large bottomwall capacitance can result due to the n/p junction region formed at the bottom of the drain extension region due to the overlap with the pocket region
9
over the entire active area. The doping in the pocket region
9
from the pocket process may be of higher concentration than the doping of the substrate
1
.
To reduce this bottomwall capacitance over the entire active area, a deeper source/drain region
10
(in this example, n-type) can be formed after formation of sidewall spacers
12
so that the bottomwall overlap of the deeper source/drain region
10
and the pocket regions
9
is eliminated, thus reducing the bottomwall capacitance in these regions as shown in
FIG. 1
b.
When dealing with sub-0.1 &mgr;m geometries, the gate width dimensions are in the 200 to 900 angstrom region, thereby leaving a channel region on the order of about 100-800 angstroms. Implants cannot be adequately controlled in accordance with the prior art semiconductor fabrication techniques when such small dimensions are involved.
REFERENCES:
patent: 5012306 (1991-04-01), Tasch, Jr. et al.
patent: 5371394 (1994-12-01), Ma et al.
patent: 5793088 (1998-08-01), Choi et al.
patent: 6051473 (2000-04-01), Ishida et al.
Tasch et al., “A New Structural Approach for Reducing Hot Carrier Generation in Deep Submicron MOSFETs,” 1990 Symposium on VLSI Technology, pp. 43-44, 1990.
Rodder et al., “Raised Source/Drain MOSFET with Dual Sidewall Spacers,” IEEE Electron Device Letters, vol. 12, No. 3, Mar. 1991, pp. 89-91.
Brady III W. James
Garner Jacqueline J.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Tran Minh Loan
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