Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-09-30
2003-12-09
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S344000, C257S408000, C438S149000, C438S479000, C438S517000
Reexamination Certificate
active
06661059
ABSTRACT:
BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates to the field of Semiconductor-On-Insulator (SOI) devices, and relates more particularly to lateral SOI PMOS devices suitable for high-voltage applications.
In fabricating high-voltage power devices, tradeoffs and compromises must typically be made in areas such as breakdown voltage, size, “on” resistance and manufacturing simplicity and reliability. Frequently, improving one parameter, such as breakdown voltage, will result in the degradation of another parameter, such as “on” resistance.
A known form of lateral thin-film SOI device includes a semiconductor substrate, a buried insulating layer on the substrate, and a lateral transistor device in an SOI layer on the buried insulating layer, with the device, such as a MOSFET, including a semiconductor surface layer on the buried insulating layer and having a source region of a first conductivity type formed in a body region of a second conductivity type opposite to that of the first, an insulated gate electrode over a channel region of the body region and insulated therefrom, a lateral drift region of the first conductivity type, and a drain region of the p-conductivity type laterally spaced apart from the source region by the drift region.
A device of this type is disclosed in U.S. Pat. No. 6,127,703, commonly-assigned with the instant application and incorporated herein by reference. The device of the aforementioned patent is a lateral SOI PMOS device having various features, such as a thin SOI layer with a linear lateral doping region and an overlying field plate, to enhance operations. This device is a p-channel or PMOS transistor, with p-type source and drain regions, manufactured using a process conventionally referred to as MOS technology. This PMOS device is configured with a heavily-doped p-type drain region, a moderately doped p-type drain buffer region, and a lightly-doped p-type drain extension region; having the drawback that all on-state current flow is forced to flow through the lightly-doped surface p-type drain extension region. This design relies on a low doping level in the p-extension to maintain a high breakdown voltage, resulting in a very high operating resistance.
The invention provides a lateral insulated gate bipolar PMOS device in which an n-type lateral drift region is provided with a linearly-graded charge profile such that the doping level in the lateral drift region increases in a direction from the drain region toward the source region, and in which a surface-adjoining n-type conductivity implant is added to the moderately-doped p-type drain buffer region and the lightly-doped p-type drain extension region; the lightly-doped drain extension region is formed throughout the surface of the n-type drift region extending from the drain towards the source, but not in direct contact with, the source region. This results in the formation of a dual-drain PMOS device in which both an n-type and a p-type terminal are available for current flow.
In a preferred embodiment of the invention, an anode is formed by implantation of SN (shallow N) into PI (p-inversion) buffer region in at least a portion of the drain region to permit an increase in total on-state current flow and reduced resistance.
In a further preferred embodiment of the invention, the conductive field plate is connected to the source region of the PMOS device.
Lateral insulated gate MOS devices in accordance with the present invention offer a significant improvement in that a combination of enhanced performance characteristics, especially, for example, current flow and on resistance, making the devices suitable for operation in a high-voltage, high-current environment, and in particular high breakdown voltage, can be achieved in a relatively simple and economical design capable of implementing PMOS structures using conventional technology.
However, the present invention recognizes that increased current flow may be provided for by implementing a MOS device having a dual current path for such current flow. These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.
REFERENCES:
patent: 6002154 (1999-12-01), Fujita
patent: 6023090 (2000-02-01), Letavic et al.
patent: 6127703 (2000-10-01), Letavic et al.
Dufort Benoit
Letavic Theodore
Petruzzello John
Biren Steven R.
Flynn Nathan J.
Koninklijke Philips Electronics , N.V.
Mandala Jr. Victor A.
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