Lateral field effect transistor and method of manufacturing the

Details Lateral field effect transistor and method of manufacturing the Lateral field effect transistor and method of manufacturing the

1997-09-09

1999-06-29

Crane, Sara

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257339, 257492, H01L 2976

Patent

active

059172177

ABSTRACT:
A lateral field effect transistor improves the trade-off relationship between the breakdown voltage and on-resistance of a lateral MOSFET integrated into a power IC. A MOSFET is formed by forming a p-type well region on a p-type substrate, and an n-type drain region accompanying an n-type offset region on the well region. A thick oxide film is disposed on the offset region. The surface concentration of the offset region is, preferably, from 5.times.10.sup.16 to 2.times.10.sup.17 cm.sup.-3 and the diffusion depth thereof is from 0.5 to 1.5 .mu.m. The maximum impurity concentration of a p-type well region is preferably adjusted to be from 5.times.10.sup.15 to 3.times.10.sup.16 cm.sup.-3. By the shallow junction depth of the offset region that promotes depletion thereof, the breakdown voltage is increased. Also, by the high maximum impurity concentration of the well region of from 5.times.10.sup.15 to 3.times.10.sup.16 cm.sup.-3, the on-resistance is lowered. Thus, the trade-off relationship between the breakdown voltage and on-resistance is improved. Specifically, the breakdown voltage is improved to 95 V and the on-resistance to 0.17 .omega.mm.sup.-2. Certain processing steps may be employed commonly to integrate the CMOS and the n-channel MOSFET into the same substrate.

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