Lateral FET structure with improved blocking voltage and on...

Details Lateral FET structure with improved blocking voltage and on... Lateral FET structure with improved blocking voltage and on...

2006-01-03

2006-01-03

Thomas, Tom (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S343000, C257S394000

Reexamination Certificate

active

06982461

ABSTRACT:
In one embodiment, a lateral FET structure (30) is formed in a body of semiconductor material (32). The structure (30) includes a plurality non-interdigitated drain regions (39) that are coupled together with a conductive layer (57), and a plurality of source regions (34) that are coupled together with a different conductive layer (51). One or more interlayer dielectrics (53,54) separate the two conductive layers (51,57). The individual source regions (34) are absent small radius fingertip regions.

REFERENCES:
patent: 5258636 (1993-11-01), Rumennik et al.
patent: 5313082 (1994-05-01), Eklund
patent: 5633521 (1997-05-01), Koishikawa
patent: 5910670 (1999-06-01), Ludikhuize
patent: 6448625 (2002-09-01), Hossain et al.
patent: 6489653 (2002-12-01), Watanabe et al.
patent: 6555883 (2003-04-01), Disney et al.

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