Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-12-03
2002-08-27
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S336000, C257S339000
Reexamination Certificate
active
06441431
ABSTRACT:
FIELD OF THE INVENTION
The instant invention pertains to a semiconductor device and more specifically to a lateral double diffused metal oxide semiconductor device.
BACKGROUND OF THE INVENTION
An ever present trend in semiconductor device manufacturing involves the reduction in size of devices while trying to reduce the power consumed by devices during both their “on” state and, more importantly, during their “off” state. However, while most devices on a circuit need to quite fast and they can have lower “on” state and “off” state power consumption, some devices which can handle higher powers need to be provided on the chip. For instance, a processor which needs an output which can run a small motor on a hard-disk drive or a processor which has an output that can run the windshield wiper motors on an automobile. The quicker devices, which typically consume less power, provide the computational power while the more rugged devices, which typically consume more power, supply the necessary voltage and power to run the exterior motors. In the past, the output of the processor was connected to a series of power devices, which were on a different chip, and the power devices would drive the motors. However, it is considerably less expensive and higher performance can be derived from having both the lower power, faster processing devices on the same substrate as the higher power, more rugged power devices (commonly referred to as intelligent power devices).
A problem with this technique is that it can be quite difficult to simultaneously fabricate the lower power, faster devices with the higher power, rugged devices. For instance, the gate dielectric on the lower power devices needs to be quite thin so that threshold voltage of the device remains low and the switching speed of the device remains quite fast, but in order to be able to handle the larger voltages of the higher power, the higher power devices need a thicker gate dielectric. In addition, power devices typically need a more complex series of doped regions so as to provide low resistance current paths without risking the chance of “latching up”.
Another problem with the integration of logic devices with the power devices involves the voltage supplied to each of the devices. Typically, the power devices require higher supply voltages so as to properly turn the devices on and to run them efficiently. It is desirable to fabricate a power device which can efficiently supply the appropriate power needed and having a higher breakdown voltage (BV) while having lower on resistance (R
sp
), lower threshold voltage (V
T
), and faster switching times.
SUMMARY OF THE INVENTION
An embodiment of the instant invention is a transistor formed on a semiconductor substrate of a first conductivity type and having an upper surface, the transistor comprising: a well region formed in the semiconductor substrate, the well region of a second conductivity type opposite that of the first conductivity type; a source region formed in the well region in the semiconductor substrate, the source region of the second conductivity type; a drain region formed in the semiconductor substrate and spaced away from the source region by a channel region, the drain region of the second. conductivity type; a conductive gate electrode disposed over the semiconductor substrate and over the channel region; a gate insulating layer disposed between the conductive gate electrode and the semiconductor substrate and having a length, the gate insulating layer comprising: a first portion of the gate insulating layer which has a first length and a first thickness; a second portion of the gate insulating layer which has a second length and a second thickness which is substantially thicker than the first thickness, the sum of the first length and the second length equalling the length of the gate insulating layer; and wherein the first portion of the gate insulating layer being situated proximate to the source region and spaced away from the drain region by the second portion of the gate insulating layer; and wherein the well region having a dopant concentration less than that of the source region and the drain region, the well region extends at least from source region towards the drain region so as to completely underlie the first portion of the gate insulating layer and to underlie at least the second portion of the gate insulating layer. Preferably, the second thickness is around 30 to 500 nm thick (more preferably around 30 to 50 nm thick—and even more preferably around 34 to 45 nm thick). The first thickness is, preferably, around 10 to 20 nm thick (more preferably around 15 nm thick).
In an alternative embodiment, the drain region is spaced away from the well region by a second region, and dopants are introduced at a first concentration into the substrate under the first portion of the gate insulating layer and are introduced into the second region at a second concentration level which is much less than the first concentration level. Preferably, the dopants have a substantially higher concentration under the first portion of the gate insulating layer than the second portion of the gate insulating layer. In another alternative embodiment, both of the source and drain regions are formed in the well region.
Another embodiment of the instant invention is a transistor formed in a semiconductor substrate of a first conductivity type and having an upper surface, the transistor comprising: a well region formed at the upper surface of the semiconductor substrate and having a second conductivity type opposite that of the first conductivity type; a source region formed at the upper surface of the semiconductor substrate and within the well region, the source region formed of the second conductivity type and spaced from an edge of the well region by a first portion of the well region, which has a length; a drain region formed of the second conductivity type at the upper surface of the semiconductor substrates, the drain region spaced from the source region by a channel region, which has a length, and spaced from the well region by a second region, which has a length; a conductive gate structure situated over the upper surface of the semiconductor substrate and extending substantially the entire length of the channel region, the conductive gate structure having a substantially constant thickness across the conductive gate structure; a gate insulating layer situated between and abutting the upper surface of the semiconductor substrate and the conductive gate structure, the gate insulating layer comprised of: a first portion of the gate insulating layer which has a first length and a first thickness, the first portion of the gate insulating layer situated over a portion of the channel region and over a portion of the first portion of the well region; and a second portion of the gate insulating layer which as a second length and a second thickness which is substantially thicker than the first thickness, a portion of the second portion of the gate insulating layer situated over the remainder of the first portion of the well region and the remainder of the second portion of the gate insulating layer situated over the second portion; and wherein the ratio of the length of the first portion of the gate insulating layer and the length of the second portion of the gate insulating layer is around 0.4 to 0.6. The length of the channel region is, preferably, equal to the summation of the length of the first portion of the well region and the length of the second region. Preferably, the well region has a dopant concentration less than the dopant concentration of the source region or the drain region. The second thickness is, preferably, around 30 to 500 nm thick (more preferably around 30 to 50 nm thick—and more preferably around 34 to 45 run thick). Preferably, the first thickness is around 10 to 20 nm thick (more preferably around 15 nm thick).
REFERENCES:
patent: 5382536 (1995-01-01), Malhi et al.
patent: 5801416 (1998-09-01), Choi et al.
patent: 6093588 (2000-07-01), De Petro et al.
Efland Taylor
Pendharkar Sameer
Tsai Chin-Yu
Brady W. James
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Thomas Tom
Tran Thien F
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