Lateral DMOS transistor with first and second drain...

Details Lateral DMOS transistor with first and second drain... Lateral DMOS transistor with first and second drain...

2001-09-20

2003-09-23

Tran, Minh Loan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S343000

Reexamination Certificate

active

06624471

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and, more particularly, to a lateral DMOS field-effect transistor.
2. Description of the Related Art
A lateral DMOS (double-diffused metal-oxide semiconductor) transistor in which the drain region has a portion with a low concentration of impurities, known as a “drift” or “drain extension” region, is known.
FIGS. 1 and 2
show, in plan and in section respectively, a transistor of this type which constitutes part of an integrated circuit formed in a silicon substrate
10
. A p-type region
11
formed in the substrate
10
constitutes the body region of the transistor. Various active areas are defined on the front surface of the substrate
10
and are insulated from one another by silicon dioxide (field oxide) plaques
12
. The plaques
12
are defined by sides
12
A such that the plaques
12
are formed in the area outside of a generally square area defined by the sides
12
A. The plaques
12
may be formed, for example, by conventional techniques for the selective oxidation of the silicon. An n-type region
13
having a low concentration of impurities and indicated N−, extends in the body region
11
partially beneath a field oxide plaque
12
and constitutes the drift region of the transistor. An n-type region
14
having a high concentration and indicated N+ extends in the region
13
, wholly occupying an active area, and constitutes the high-concentration portion of the drain region. A metal element
15
in contact with the region
14
constitutes the drain electrode D of the transistor. Another high-concentration n-type region
16
extends in the body region
11
and delimits, with the region
13
, a channel
17
. A metal element
18
in contact with the region
16
constitutes the source electrode S of the transistor. A strip
19
of electrically conductive material, for example, doped polycrystalline silicon, extends over the channel region and over a portion of the drift region
13
to form the gate electrode of the transistor. This strip is separated from the front surface of the substrate
10
by a thin layer
9
of insulating material which constitutes the gate dielectric. The strip
19
also extends partially over the plaque
12
which separates the two active areas in which the transistor is formed and, on top of the strip
19
, there is a metal contact element
20
of the gate G. A p-type region
21
with a high concentration of impurities extends in the body region
11
to ensure an ohmic contact between this region and a metal element
22
which constitutes the body electrode B of the transistor.
As is known, when a voltage above a predetermined threshold is applied between the gate and body electrodes, the conductivity of the channel, that is, of the portion of the body region
11
beneath the gate electrode, is reversed so that a current can pass between the source electrode
18
and the drain electrode
15
. In these conditions, the drift region
13
acts as a resistance distributed between the drain electrode
15
and the channel region
17
so that the potential of the drain region in the vicinity of the channel is lower than the drain-electrode potential.
This transistor can be formed by the same method as is used for conventional MOS and CMOS transistors of low-voltage logic circuits (2-3V) but, by virtue of the characteristic described above, can be used with higher supply voltages (7-8V). Some circuits which have to be supplied with high voltages, for example, control circuits for non-volatile memories, can therefore be produced with a smaller number of components and hence in smaller areas of the integrated circuit with the use of transistors of this type.
However, it is not possible to make the best use of the advantageous characteristics of the transistor described above because the voltage drop in the drift region when the transistor is conducting cannot be evaluated precisely at the stage of the design of the integrated circuit, because of the variability of the production parameters. To avoid the risk of the electric field formed between the gate electrode
19
and the drift region
13
in the vicinity of the channel
17
adopting values which are dangerous to the integrity of the gate dielectric
9
, the device therefore has to be designed with quite large safety margins.
BRIEF SUMMARY OF THE INVENTION
An embodiment of the present invention directed to a lateral DMOS transistor which does not have the limitations described above.
The lateral DMOS transistor includes a substrate of semiconductor material having a front surface; a source region with a second type of conductivity extending in the substrate from the front surface; and a drain region with the second type of conductivity extending in the substrate from the front surface and delimiting one side of a channel region that is delimited on an opposite side by the source region. The drain region includes a first highly doped region spaced apart from the channel region and a relatively lightly doped drift region that extends from the channel region to the first highly doped region. The later DMOS transistor also includes a first drain electrode in contact with the first highly doped region of the drain region and a second drain electrode in contact with the drift region of the drain region.


REFERENCES:
patent: 4977434 (1990-12-01), Delagebeaudeuf et al.
patent: 6002301 (1999-12-01), Sugimura et al.
patent: 6303961 (2001-10-01), Shibib
patent: 0 019 560 (1980-11-01), None
patent: 0 035 453 (1981-09-01), None
patent: 0 267 768 (1988-05-01), None

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