Lateral DMOS transistor with a self-aligned drain region

Details Lateral DMOS transistor with a self-aligned drain region Lateral DMOS transistor with a self-aligned drain region

2003-07-11

2004-11-30

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S492000, C257S493000

Reexamination Certificate

active

06825531

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to LDMOS transistor structures and, in particular, to a method for forming an LDMOS transistor with reduced conduction and switching losses.
DESCRIPTION OF THE RELATED ART
FIG. 1
is a cross-sectional view of a conventional N-type lateral double-diffused MOS (LDMOS) transistor. In general, LDMOS transistor
10
includes a polysilicon gate
12
, an N+ source region
14
formed in a P-type body region
16
, and an N+ drain region
18
. Polysilicon gate
12
is insulated from the semiconductor substrate by a thin gate oxide layer. Drain region
18
can be formed in an N-well
17
or in a more heavily doped N-type region, such as an N-Drift region
15
. A P+ diffusion region
13
is usually included for making electrical contact to body region
16
.
In LDMOS transistor
10
, source region
14
and body region
16
are self-aligned to the left edge of polysilicon gate
12
. That is, during the fabrication process to form LDMOS transistor
10
, polysilicon gate
12
is defined and then the source region implantation and the body region implantation are preformed using the polysilicon gate as a mask. As thus implanted, the source region dopants and the body region dopants are aligned to the left edge of polysilicon gate
12
. After subsequent heat treatments to diffuse the dopants and anneal the silicon substrate, N+ source region
14
and body region
16
as shown in
FIG. 1
are formed.
However, at the drain side of LDMOS transistor
10
, the diffusion regions, such as the drain region, and the drain contact structures, such as the drain contact, are not self-aligned to the right edge of the polysilicon gate. When N-Drift region
15
is included, the N-drift region can be formed self-aligned to the right edge of the polysilicon gate. However, drain region
18
is formed spaced apart from the right edge of polysilicon gate
12
to form a drift region between body region
16
and heavily doped N+ drain region
18
. Furthermore, a drain contact
11
for making electrical contact to drain region
18
is formed above the drain diffusion region. The contact opening is also made without self-alignment to the polysilicon gate.
Because the N+ drain region and the drain contact opening are not self-aligned, drain region
18
has to be spaced sufficiently apart from the right edge of polysilicon gate
12
to meet lithography requirements for misalignment tolerance. Furthermore, the distance between polysilicon gate
12
and drain region
18
is also selected to meet the desired gate to drain breakdown voltage requirements, the longer the distance, the larger the breakdown voltage. Due to the misalignment tolerance and breakdown voltage requirements, a lower limit is placed on the distance B between polysilicon gate
12
and drain region
18
and distance B cannot be readily minimized. As a result, the conventional LDMOS transistor has a higher cell pitch. Higher cell pitch is undesirable because it results in a higher device resistance (R
DS
) as the distance between the drain and the source of the transistor is larger. Higher cell pitch is also undesirable because the resultant transistor device consumes more silicon area and thus is more costly to fabricate.
In some conventional LDMOS transistors, the polysilicon gate is extended so that the drain region can be formed self-aligned to the edge of the polysilicon gate. However, such LDMOS structures are undesirable because the poly to drain breakdown voltage becomes very low because of the thin gate oxide layer that separates the polysilicon gate from the drain diffusion region.
In the LDMOS transistor of
FIG. 1
, an N-Drift diffusion region
15
is included at the drain side of the device. Typically, the N-Drift region is more heavily doped than N-well
17
and functions to lower the device resistance (R
DS
) of the LDMOS transistor. However, N-Drift region
15
is included typically at the expense of a lower breakdown voltage between the p-type body region and the N-type drain drift region. Specifically, the breakdown voltage between the body and the drain drift region is determined by the doping of the more heavily doped side. Since N-Drift diffusion region is more heavily doped than N-well, when N-Drift diffusion region is included in the LDMOS transistor, the breakdown voltage between the body and the drift region is lowered. For example, the breakdown voltage between the body region and the N-well can be on the order of 80 volts above while the breakdown voltage between the body region and the N-Drift can be only about 20 volts.
It is generally desirable to reduce the device resistance R
DS
and also the cell pitch of an LDMOS transistor. The device resistance R
DS
includes the resistance of the source metal line connected to the source region, the source contact resistance, the source region resistance, the channel resistance, the drain region resistance, the resistance of the drain metal line connected to the drain region, and the drain contact resistance. To reduce the device resistance of an LDMOS transistor, it is often necessary to reduce the dimensions of the structures in the LDMOS transistor.
Typically, the resistance of the drain region contributes to about 30-40% of the total device resistance and the channel resistance contributes to about another 30%. Therefore, to reduce the device resistance, it is sometimes desirable to reduce the polysilicon length of the LDMOS transistor. However, there is a limit as to how much the polysilicon gate length can be scaled down due to limitations from photo-lithography technology. This is because in the self-aligned process to form the source region and the body region, the photoresist mask for the source and the body implantation is formed centered or with minimum overlap rule for misalignment on the polysilicon gate. If the length of the polysilicon gate is reduced too much, there may not be enough room for the mask to align properly on the top of polysilicon. Thus, the polysilicon gate has to have a minimum length to meet the lithography requirement for the placement of the mask on the polysilicon gate to allow sufficient room for misalignment.
It is desirable to provide an LDMOS transistor with reduced device resistance, reduced device pitch, including reduction of the channel length of the LDMOS transistor.
SUMMARY OF THE INVENTION
According to one embodiment of the present invention, an LDMOS transistor includes a body region, a source region, a conductive gate, an alignment structure and a drain region. The body region is of a first conductivity type and formed in a semiconductor layer of a second conductivity type. The source region is of the second conductivity type and formed in the body region. The conductive gate is insulated from the semiconductor layer by a first dielectric layer and overlies the body region. The source region is formed self-aligned to a first edge of the conductive gate. The alignment structure is formed adjacent a second edge, opposite the first edge, of the conductive gate. The alignment structure has a first edge in proximity to the second edge of the conductive gate. The drain region is of the second conductivity type and formed in the semiconductor layer self-aligned to the second edge, opposite the first edge, of the alignment structure.
In one embodiment, the conductive gate is formed by a first polysilicon layer and the alignment structure is formed by a second polysilicon layer. In another embodiment, the alignment structure is a silicon nitride layer.
The incorporation of the alignment structure in the LDMOS transistor of the present invention enables self-aligned drain region and/or drain contact opening to be formed.
The present invention is better understood upon consideration of the detailed description below and the accompanying drawings.


REFERENCES:
Shuming Xu et al., “High Power Silicon RF LDMOSFET Technology for 2.1GHz Power Amplifier Applications”, ISPSD 2003, Apr. 14-17, Cambridge, UK, pp. 190-193.

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